loadpatents
name:-0.0081520080566406
name:-0.01620888710022
name:-0.0011758804321289
Hirata; Erick M. Patent Filings

Hirata; Erick M.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Hirata; Erick M..The latest application filed is for "digitally calibrated high speed clock distribution".

Company Profile
0.13.8
  • Hirata; Erick M. - Torrance CA
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Digitally calibrated high speed clock distribution
Grant 8,179,173 - Hirata , et al. May 15, 2
2012-05-15
Digitally Calibrated High Speed Clock Distribution
App 20110221486 - Hirata; Erick M. ;   et al.
2011-09-15
DNL/INL trim techniques for comparator based analog to digital converters
Grant 7,154,421 - Devendorf , et al. December 26, 2
2006-12-26
Low power output driver
Grant 7,098,700 - Martinez , et al. August 29, 2
2006-08-29
Digitally trimmed DAC cell
Grant 7,095,347 - Hirata , et al. August 22, 2
2006-08-22
On-chip multilayer metal shielded transmission line
Grant 6,975,189 - Reamon , et al. December 13, 2
2005-12-13
DNL/INL trim techniques for comparator based analog to digital converters
App 20050128118 - Devendorf, Don C. ;   et al.
2005-06-16
Low power output driver
App 20050127955 - Martinez, Nanci ;   et al.
2005-06-16
Split cell bowtie digital to analog converter and method
Grant 6,879,276 - Devendorf , et al. April 12, 2
2005-04-12
Substraction circuit with a dummy digital to analog converter
App 20050038846 - Devendorf, Don C. ;   et al.
2005-02-17
Split Cell Bowtie Digital To Analog Converter And Method
App 20050035892 - Devendorf, Don C. ;   et al.
2005-02-17
Clamped comparator
App 20050035788 - Devendorf, Don C. ;   et al.
2005-02-17
Trickle current-cascode DAC
App 20040257125 - Cheng, William W. ;   et al.
2004-12-23
Digitally trimmed DAC cell
App 20040257058 - Hirata, Erick M. ;   et al.
2004-12-23
High-performance track and hold circuit
Grant 6,825,697 - Linder , et al. November 30, 2
2004-11-30
Advanced digital antenna module
Grant 6,768,442 - Meyers , et al. July 27, 2
2004-07-27
Monolithic circuit and method for adding a randomized dither signal to the fine quantizer element of a subranging analog-to digital converter (ADC)
Grant 5,990,815 - Linder , et al. November 23, 1
1999-11-23
Test circuit and method of trimming a unary digital-to-analog converter (DAC) in a subranging analog-to-digital converter (ADC)
Grant 5,973,631 - McMullen , et al. October 26, 1
1999-10-26
Current feedback differential amplifier clamp
Grant 5,859,569 - Le , et al. January 12, 1
1999-01-12
Temperature compensated amplifier
Grant 5,859,568 - Le , et al. January 12, 1
1999-01-12
Mixer structures with enhanced conversion gain and reduced spurious signals
Grant 5,859,559 - Hong , et al. January 12, 1
1999-01-12

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.

© 2024 USPTO.report | Privacy Policy | Resources | RSS Feed of Trademarks | Trademark Filings Twitter Feed