Hirashita; Norio

Patent Applications and Registrations

Patent applications and USPTO patent grants for Hirashita; Norio.The latest application filed is for "semiconductor device having low parasitic resistance and small junction leakage characteristic and method of manufacturing the same".

Company Profile

0.8.9

Hirashita; Norio - Tokyo JP
Hirashita; Norio - Higashiyamato JP
Hirashita; Norio - Higashiyamato-shi JP
Hirashita; Norio - Higashi-yamato JP

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Semiconductor device having silicide layer completely occupied amorphous layer formed in the substrate and an interface junction of (111) silicon plane Grant 8,183,643 - Ichimori , et al. May 22, 2	2012-05-22
Semiconductor device having low parasitic resistance and small junction leakage characteristic and method of manufacturing the same App 20110223724 - Ichimori; Takashi ; et al.	2011-09-15
Semiconductor device and method of manufacturing the same Grant 7,759,228 - Sugiyama , et al. July 20, 2	2010-07-20
Structure of a field effect transistor having metallic silicide and manufacturing method thereof Grant 7,479,682 - Hirashita , et al. January 20, 2	2009-01-20
Structure of a field effect transistor having metallic silicide and manufacturing method thereof Grant 7,244,996 - Hirashita , et al. July 17, 2	2007-07-17
Structure of a field effect transistor having metallic silicide and manufacturing method thereof App 20070158757 - Hirashita; Norio ; et al.	2007-07-12
Method of manufacturing semiconductor device Grant 7,199,030 - Ikeda , et al. April 3, 2	2007-04-03
Semiconductor device and method of manufacturing the same App 20060281234 - Sugiyama; Naoharu ; et al.	2006-12-14
Semiconductor device having low parasitic resistance and small junction leakage characteristic App 20060145271 - Ichimori; Takashi ; et al.	2006-07-06
Method of manufacturing a semiconductor device Grant 6,861,322 - Hirashita , et al. March 1, 2	2005-03-01
SOI MOS field effect transistor and manufacturing method therefor Grant 6,750,088 - Hirashita , et al. June 15, 2	2004-06-15
Method of manufacturing semiconductor device App 20040067626 - Ikeda, Satoshi ; et al.	2004-04-08
SOI MOS field effect transistor and manufacturing method therefor App 20030151094 - Hirashita, Norio ; et al.	2003-08-14
Method of manufacturing a semiconductor device App 20020182784 - Hirashita, Norio ; et al.	2002-12-05
Semiconductor device having low parasitic resistance and small junction leakage characteristic and method of manufacturing the same App 20020036320 - Ichimori, Takashi ; et al.	2002-03-28
Structure of a field effect transistor having metallic silicide and manufacturing method thereof App 20010028087 - Hirashita, Norio ; et al.	2001-10-11
Structure of a semiconductor chip having a conductive layer Grant 5,288,948 - Fukuda , et al. February 22, 1	1994-02-22

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.