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name:-0.0075259208679199
name:-0.0057239532470703
name:-0.0006258487701416
Hirabayashi; Keisuke Patent Filings

Hirabayashi; Keisuke

Patent Applications and Registrations

Patent applications and USPTO patent grants for Hirabayashi; Keisuke.The latest application filed is for "method of processing dummy pattern based on boundary length and density of wiring pattern, semiconductor design apparatus and semiconductor device".

Company Profile
0.5.6
  • Hirabayashi; Keisuke - Kanagawa N/A JP
  • Hirabayashi; Keisuke - Toyohashi JP
  • Hirabayashi; Keisuke - Aichi JP
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Method of processing dummy pattern based on boundary length and density of wiring pattern, semiconductor design apparatus and semiconductor device
Grant 8,365,127 - Hirabayashi January 29, 2
2013-01-29
Method Of Processing Dummy Pattern Based On Boundary Length And Density Of Wiring Pattern, Semiconductor Design Apparatus And Semiconductor Device
App 20120199979 - HIRABAYASHI; Keisuke
2012-08-09
Method of processing dummy pattern based on boundary length and density of wiring pattern, semiconductor design apparatus and semiconductor device
Grant 8,181,142 - Hirabayashi May 15, 2
2012-05-15
Method of processing dummy pattern based on boundary length and density of wiring pattern, semiconductor design apparatus and semiconductor device
Grant 7,900,177 - Hirabayashi March 1, 2
2011-03-01
Method of processing dummy pattern based on boundary length and density of wiring pattern, semiconductor design apparatus and semiconductor device
App 20100327467 - Hirabayashi; Keisuke
2010-12-30
Method, device, and program for predicting a manufacturing defect part of a semiconductor device
App 20100131915 - Hirabayashi; Keisuke
2010-05-27
Ultrasonic sensor comprising a metal/ferroelectric/metal/insulator/semiconductor structure
Grant 7,692,257 - Ishida , et al. April 6, 2
2010-04-06
Integrated Device
App 20090278212 - Ishida; Makoto ;   et al.
2009-11-12
Method of processing dummy pattern based on boundary length and density of wiring pattern, semiconductor design apparatus and semiconductor device
App 20080179754 - Hirabayashi; Keisuke
2008-07-31
Semiconductor element, semiconductor sensor and semiconductor memory element
App 20060278907 - Ishida; Makoto ;   et al.
2006-12-14

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