| Patent | Date |
|---|
Device, Method And System For Providing A Stacked Arrangement Of Integrated Circuit Dies
App 20220271022 - GOMES; Wilfred ; et al. | 2022-08-25 |
Device, method and system for providing a stacked arrangement of integrated circuit dies
Grant 11,373,987 - Gomes , et al. June 28, 2 | 2022-06-28 |
Dynamic partial power down of memory-side cache in a 2-level memory hierarchy
Grant 11,200,176 - Ramanujan , et al. December 14, 2 | 2021-12-14 |
Apparatus and method for implementing a multi-level memory hierarchy having different operating modes
Grant 11,132,298 - Ramanujan , et al. September 28, 2 | 2021-09-28 |
Device, Method And System For Providing A Stacked Arrangement Of Integrated Circuit Dies
App 20210074695 - GOMES; Wilfred ; et al. | 2021-03-11 |
Dynamic Partial Power Down Of Memory-side Cache In A 2-level Memory Hierarchy
App 20210056035 - RAMANUJAN; Raj K. ; et al. | 2021-02-25 |
Dynamic partial power down of memory-side cache in a 2-level memory hierarchy
Grant 10,795,823 - Ramanujan , et al. October 6, 2 | 2020-10-06 |
Apparatus and method for implementing a multi-level memory hierarchy
Grant 10,719,443 - Ramanujan , et al. | 2020-07-21 |
Methods and apparatus to suspend and resume computing systems
Grant 10,564,986 - Rothman , et al. Feb | 2020-02-18 |
Two-level System Main Memory
App 20190243558 - Dahlen; Eric J. ; et al. | 2019-08-08 |
Two-level system main memory
Grant 10,365,832 - Dahlen , et al. July 30, 2 | 2019-07-30 |
Apparatus And Method For Implementing A Multi-level Memory Hierarchy
App 20190220406 - RAMANUJAN; Raj K. ; et al. | 2019-07-18 |
Apparatus and method for implementing a multi-level memory hierarchy
Grant 10,241,912 - Ramanujan , et al. | 2019-03-26 |
Apparatus And Method For Implementing A Multi-level Memory Hierarchy Having Different Operating Modes
App 20180341588 - RAMANUJAN; Raj K. ; et al. | 2018-11-29 |
Apparatus and method for implementing a multi-level memory hierarchy having different operating modes
Grant 10,102,126 - Ramanujan , et al. October 16, 2 | 2018-10-16 |
Replacement of a block with a compressed block to increase capacity of a memory-side cache
Grant 10,048,868 - Alameldeen , et al. August 14, 2 | 2018-08-14 |
Methods And Apparatus To Suspend And Resume Computing Systems
App 20180181411 - Rothman; Michael A. ; et al. | 2018-06-28 |
Selective Data Compression/decompression For Intermemory Transfer Interface
App 20180095674 - ALAMELDEEN; Alaa R. ; et al. | 2018-04-05 |
Using Compression To Increase Capacity Of A Memory-side Cache With Large Block Size
App 20180088822 - Alameldeen; Alaa R. ; et al. | 2018-03-29 |
Two-level System Main Memory
App 20180004432 - DAHLEN; Eric J. ; et al. | 2018-01-04 |
Apparatus And Method For Implementing A Multi-level Memory Hierarchy
App 20170249250 - RAMANUJAN; Raj K. ; et al. | 2017-08-31 |
Instruction emulation processors, methods, and systems
Grant 9,703,562 - Rash , et al. July 11, 2 | 2017-07-11 |
Two-level system main memory
Grant 9,690,493 - Dahlen , et al. June 27, 2 | 2017-06-27 |
Apparatus and method for implementing a multi-level memory hierarchy
Grant 9,600,416 - Ramanujan , et al. March 21, 2 | 2017-03-21 |
Controlling non-redundant execution in a redundant multithreading (RMT) processor
Grant 9,594,648 - Hinton , et al. March 14, 2 | 2017-03-14 |
Apparatus And Method For Implementing A Multi-level Memory Hierarchy Having Different Operating Modes
App 20170031821 - RAMANUJAN; Raj K. ; et al. | 2017-02-02 |
Method and apparatus for store durability and ordering in a persistent memory architecture
Grant 9,423,959 - Dulloor , et al. August 23, 2 | 2016-08-23 |
Bad block management mechanism
Grant 9,418,700 - Ramanujan , et al. August 16, 2 | 2016-08-16 |
Apparatus and method for implementing a multi-level memory hierarchy having different operating modes
Grant 9,378,142 - Ramanujan , et al. June 28, 2 | 2016-06-28 |
Two-level System Main Memory
App 20160041772 - Dahlen; Eric J. ; et al. | 2016-02-11 |
Adaptive queuing of a cache for a processing element
Grant 9,146,873 - Vasudevan , et al. September 29, 2 | 2015-09-29 |
Two-level system main memory
Grant 9,087,584 - Dahlen , et al. July 21, 2 | 2015-07-21 |
Obtaining data for redundant multithreading (RMT) execution
Grant 9,081,688 - Hinton , et al. July 14, 2 | 2015-07-14 |
Opcode Trapping
App 20150186140 - Toll; Bret L. ; et al. | 2015-07-02 |
Processor having execution core sections operating at different clock rates
Grant RE45,487 - Sager , et al. April 21, 2 | 2015-04-21 |
Method And Apparatus For Store Durability And Ordering In A Persistent Memory Architecture
App 20150006834 - DULLOOR; Subramanya R. ; et al. | 2015-01-01 |
Machine Check Architecture Execution Environment For Non-microcoded Processor
App 20140380085 - Rash; Willam C. ; et al. | 2014-12-25 |
Two-level System Main Memory
App 20140351660 - DAHLEN; Eric J. ; et al. | 2014-11-27 |
Metadata Management And Support For Phase Change Memory With Switch (pcms)
App 20140317337 - Puthiyedath; Leena K. ; et al. | 2014-10-23 |
Dynamic Partial Power Down Of Memory-side Cache In A 2-level Memory Hierarchy
App 20140304475 - Ramanujan; Raj K ; et al. | 2014-10-09 |
Systems And Methods For Implementing Transactional Memory
App 20140281236 - Rash; William C. ; et al. | 2014-09-18 |
Instruction Emulation Processors, Methods, And Systems
App 20140281399 - RASH; WILLIAM C. ; et al. | 2014-09-18 |
Redundant multithreading processor
Grant 8,793,689 - Hinton , et al. July 29, 2 | 2014-07-29 |
Bad Block Management Mechanism
App 20140006848 - RAMANUJAN; RAJ K. ; et al. | 2014-01-02 |
Two-level system main memory
Grant 8,612,676 - Dahlen , et al. December 17, 2 | 2013-12-17 |
Apparatus And Method For Implementing A Multi-level Memory Hierarchy Having Different Operating Modes
App 20130268728 - Ramanujan; Raj K. ; et al. | 2013-10-10 |
Adaptive Queuing of a Cache for a Processing Element
App 20130262718 - Vasudevan; Anil ; et al. | 2013-10-03 |
Processor having execution core sections operating at different clock rates
Grant RE44,494 - Sager , et al. September 10, 2 | 2013-09-10 |
Method and apparatus for quick resumption
Grant 8,407,489 - Rothman , et al. March 26, 2 | 2013-03-26 |
Two-level System Main Memory
App 20120166891 - Dahlen; Eric J. ; et al. | 2012-06-28 |
Method and system to perform caching based on file-level heuristics
Grant 8,171,219 - Trika , et al. May 1, 2 | 2012-05-01 |
Processor Having Execution Core Sections Operating At Different Clock Rates
App 20120042151 - Sager; David J. ; et al. | 2012-02-16 |
Redundant Multithreading Processor
App 20110307894 - Hinton; Glenn J. ; et al. | 2011-12-15 |
Method And System To Perform Caching Based On File-level Heuristics
App 20100250834 - Trika; Sanjeev N. ; et al. | 2010-09-30 |
Controlling non-redundant execution in a redundant multithreading (RMT) processor
App 20100169628 - Hinton; Glenn J. ; et al. | 2010-07-01 |
Obtaining data for redundant multithreading (RMT) execution
App 20100169582 - Hinton; Glenn J. ; et al. | 2010-07-01 |
Method and apparatus for quick resumption
App 20090271641 - Rothman; Michael A. ; et al. | 2009-10-29 |
Method and apparatus for quick resumption
Grant 7,523,323 - Rothman , et al. April 21, 2 | 2009-04-21 |
Method and apparatus for quick resumption where the system may forego initialization of at least one memory range identified in the resume descriptor
Grant 7,480,791 - Rothman , et al. January 20, 2 | 2009-01-20 |
Fusing load and alu operations
Grant 7,398,372 - Samra , et al. July 8, 2 | 2008-07-08 |
Method and apparatus for staggering execution of an instruction
Grant 7,366,881 - Roussel , et al. April 29, 2 | 2008-04-29 |
Method and apparatus for quick resumption
App 20070061556 - Rothman; Michael A. ; et al. | 2007-03-15 |
Method and apparatus for quick resumption
App 20070061558 - Rothman; Michael A. ; et al. | 2007-03-15 |
Method and apparatus for staggering execution of an instruction
App 20050251645 - Roussel, Patrice ; et al. | 2005-11-10 |
Staggering execution of a single packed data instruction using the same circuit
Grant 6,925,553 - Roussel , et al. August 2, 2 | 2005-08-02 |
Processor having replay architecture with fast and slow replay paths
Grant 6,735,688 - Upton , et al. May 11, 2 | 2004-05-11 |
Staggering execution of a single packed data instruction using the same circuit
App 20040083353 - Roussel, Patrice ; et al. | 2004-04-29 |
Unaligned memory operands
Grant 6,721,866 - Roussel , et al. April 13, 2 | 2004-04-13 |
Method and apparatus for staggering execution of a single packed data instruction using the same circuit
Grant 6,694,426 - Roussel , et al. February 17, 2 | 2004-02-17 |
Method and apparatus for staggering execution of a single packed data instruction using the same circuit
Grant 6,687,810 - Roussel , et al. February 3, 2 | 2004-02-03 |
Fusing load and alu operations
App 20030236966 - Samra, Nicholas G. ; et al. | 2003-12-25 |
Unaligned memory operands
App 20030120889 - Roussel, Patrice ; et al. | 2003-06-26 |
Method and apparatus for staggering execution of a single packed data instruction using the same circuit
App 20020184474 - Roussel, Patrice ; et al. | 2002-12-05 |
Method and apparatus for staggering execution of a single packed data instruction using the same circuit
App 20020178348 - Roussel, Patrice ; et al. | 2002-11-28 |
Way-predicting cache memory
Grant 6,425,055 - Sager , et al. July 23, 2 | 2002-07-23 |
Method and apparatus for staggering execution of an instruction
Grant 6,425,073 - Roussel , et al. July 23, 2 | 2002-07-23 |
Apparatus for issuing instructions and reissuing a previous instructions by recirculating using the delay circuit
Grant 6,378,061 - Carbine , et al. April 23, 2 | 2002-04-23 |
Method and apparatus for staggering execution of an instruction
App 20010034826 - Roussel, Patrice ; et al. | 2001-10-25 |
Processor having execution core sections operating at different clock rates
App 20010029590 - Sager, David J. ; et al. | 2001-10-11 |
Method and apparatus for staggering execution of a single packed data instruction using the same circuit
Grant 6,230,257 - Roussel , et al. May 8, 2 | 2001-05-08 |
Processor having execution core sections operating at different clock rates
Grant 6,216,234 - Sager , et al. April 10, 2 | 2001-04-10 |
Checking data type of operands specified by an instruction using attributes in a tagged array architecture
Grant 6,185,671 - Pentovski , et al. February 6, 2 | 2001-02-06 |
Trace based instruction caching
Grant 6,170,038 - Krick , et al. January 2, 2 | 2001-01-02 |
Method and apparatus for providing a cache management technique
Grant 6,105,111 - Hammarlund , et al. August 15, 2 | 2000-08-15 |
Processor that redirects an instruction fetch pipeline immediately upon detection of a mispredicted branch while committing prior instructions to an architectural state
Grant 6,079,014 - Papworth , et al. June 20, 2 | 2000-06-20 |
Flag renaming and flag masks within register alias table
Grant 6,047,369 - Colwell , et al. April 4, 2 | 2000-04-04 |
Trace based instruction caching
Grant 6,018,786 - Krick , et al. January 25, 2 | 2000-01-25 |
Method and apparatus for implementing a branch target buffer in CISC processor
Grant 5,903,751 - Hoyt , et al. May 11, 1 | 1999-05-11 |
Method and apparatus for blocking execution of and storing load operations during their execution
Grant 5,881,262 - Abramson , et al. March 9, 1 | 1999-03-09 |
Computer system employing streaming buffer for instruction preetching
Grant 5,870,599 - Hinton , et al. February 9, 1 | 1999-02-09 |
Method and apparatus for calculating effective memory addresses
Grant 5,860,154 - Abramson , et al. January 12, 1 | 1999-01-12 |
Dual instruction buffers with a bypass bus and rotator for a decoder of multiple instructions of variable length
Grant 5,845,100 - Gupta , et al. December 1, 1 | 1998-12-01 |
Circuit and method for scheduling instructions by predicting future availability of resources required for execution
Grant 5,842,036 - Hinton , et al. November 24, 1 | 1998-11-24 |
Processor having execution core sections operating at different clock rates
Grant 5,828,868 - Sager , et al. October 27, 1 | 1998-10-27 |
Register alias table update to indicate architecturally visible state
Grant 5,826,094 - Colwell , et al. October 20, 1 | 1998-10-20 |
Method and apparatus for performing multiple load operations to the same memory location in a computer system
Grant 5,826,109 - Abramson , et al. October 20, 1 | 1998-10-20 |
Dual prediction branch system having two step of branch recovery process which activated only when mispredicted branch is the oldest instruction in the out-of-order unit
Grant 5,812,839 - Hoyt , et al. September 22, 1 | 1998-09-22 |
Method and apparatus for changing flow of control in a processor
Grant 5,809,271 - Colwell , et al. September 15, 1 | 1998-09-15 |
Circuit and method for scheduling instructions by predicting future availability of resources required for execution
Grant 5,809,325 - Hinton , et al. September 15, 1 | 1998-09-15 |
Method and apparatus for dynamic allocation of multiple buffers in a processor
Grant 5,778,245 - Papworth , et al. July 7, 1 | 1998-07-07 |
Method and apparatus for processing memory-type information within a microprocessor
Grant 5,751,996 - Glew , et al. May 12, 1 | 1998-05-12 |
Out-of-order processor with a memory subsystem which handles speculatively dispatched load operations
Grant 5,751,983 - Abramson , et al. May 12, 1 | 1998-05-12 |
Computer system that maintains processor ordering consistency by snooping an external bus for conflicts during out of order execution of memory access instructions
Grant 5,748,937 - Abramson , et al. May 5, 1 | 1998-05-05 |
Method and apparatus for blocking execution of and storing load operations during their execution
Grant 5,724,536 - Abramson , et al. March 3, 1 | 1998-03-03 |
Method for pipeline processing of instructions by controlling access to a reorder buffer using a register file outside the reorder buffer
Grant 5,721,855 - Hinton , et al. February 24, 1 | 1998-02-24 |
Method and apparatus for dispatching and executing a load operation to memory
Grant 5,717,882 - Abramson , et al. February 10, 1 | 1998-02-10 |
Method and apparatus for handling code segment violations in a computer system
Grant 5,708,843 - Abramson , et al. January 13, 1 | 1998-01-13 |
Method and apparatus for performing load operations in a computer system
Grant 5,694,574 - Abramson , et al. December 2, 1 | 1997-12-02 |
Method and apparatus for binding instructions to dispatch ports of a reservation station
Grant 5,689,674 - Griffith , et al. November 18, 1 | 1997-11-18 |
Method and apparatus for maintaining a macro instruction for refetching in a pipelined processor
Grant 5,687,338 - Boggs , et al. November 11, 1 | 1997-11-11 |
Cache memory system having data and tag arrays and multi-purpose buffer assembly with multiple line buffers
Grant 5,680,572 - Akkary , et al. October 21, 1 | 1997-10-21 |
Methods and apparatus for caching data in a non-blocking manner using a plurality of fill buffers
Grant 5,671,444 - Akkary , et al. September 23, 1 | 1997-09-23 |
Method and apparatus for executing and dispatching store operations in a computer system
Grant 5,664,137 - Abramson , et al. September 2, 1 | 1997-09-02 |
Speculative and committed resource files in an out-of-order processor
Grant 5,627,985 - Fetterman , et al. May 6, 1 | 1997-05-06 |
Computer system and method for maintaining memory consistency in a pipelined, non-blocking caching bus request queue
Grant 5,623,628 - Brayton , et al. April 22, 1 | 1997-04-22 |
Translation lookaside buffer that is non-blocking in response to a miss for use within a microprocessor capable of processing speculative instructions
Grant 5,613,083 - Glew , et al. March 18, 1 | 1997-03-18 |
Method and apparatus for signalling a store buffer to output buffered store data for a load operation on an out-of-order execution computer system
Grant 5,606,670 - Abramson , et al. February 25, 1 | 1997-02-25 |
Method and apparatus for performing error correction on data from an external memory
Grant 5,604,753 - Bauer , et al. February 18, 1 | 1997-02-18 |
Method and apparatus for resolving return from subroutine instructions in a computer processor
Grant 5,604,877 - Hoyt , et al. February 18, 1 | 1997-02-18 |
Methods and apparatus for fordwarding buffered store data on an out-of-order execution computer system
Grant 5,588,126 - Abramson , et al. December 24, 1 | 1996-12-24 |
Method and apparatus for state recovery following branch misprediction in an out-of-order microprocessor
Grant 5,586,278 - Papworth , et al. December 17, 1 | 1996-12-17 |
Entry allocation in a circular buffer using wrap bits indicating whether a queue of the circular buffer has been traversed
Grant 5,584,038 - Papworth , et al. December 10, 1 | 1996-12-10 |
Branch target buffer for dynamically predicting branch instruction outcomes using a predicted branch history
Grant 5,584,001 - Hoyt , et al. December 10, 1 | 1996-12-10 |
Entry allocation in a circular buffer
Grant 5,584,037 - Papworth , et al. December 10, 1 | 1996-12-10 |
Method and apparatus for loading and storing misaligned data on an out-of-order execution computer system
Grant 5,577,200 - Abramson , et al. November 19, 1 | 1996-11-19 |
Hybrid execution unit for complex microprocessor
Grant 5,574,942 - Colwell , et al. November 12, 1 | 1996-11-12 |
Method and apparatus for implementing a set-associative branch target buffer
Grant 5,574,871 - Hoyt , et al. November 12, 1 | 1996-11-12 |
Method and apparatus for zero extension and bit shifting to preserve register parameters in a microprocessor utilizing register renaming
Grant 5,564,056 - Fetterman , et al. October 8, 1 | 1996-10-08 |
Method and apparatus for implementing a non-blocking translation lookaside buffer
Grant 5,564,111 - Glew , et al. October 8, 1 | 1996-10-08 |
Methods and apparatus for determining memory operating characteristics for given memory locations via assigned address ranges
Grant 5,561,814 - Glew , et al. October 1, 1 | 1996-10-01 |
Circuit and method for scheduling instructions by predicting future availability of resources required for execution
Grant 5,555,432 - Hinton , et al. September 10, 1 | 1996-09-10 |
Apparatus for pipeline streamlining where resources are immediate or certainly retired
Grant 5,553,256 - Fetterman , et al. September 3, 1 | 1996-09-03 |
Ready selection of data dependent instructions using multi-cycle cams in a processor performing out-of-order instruction execution
Grant 5,546,597 - Martell , et al. August 13, 1 | 1996-08-13 |
Method and apparatus for implementing a single clock cycle line replacement in a data cache unit
Grant 5,526,510 - Akkary , et al. June 11, 1 | 1996-06-11 |
Method and apparatus for scheduling the dispatch of instructions from a reservation station
Grant 5,519,864 - Martell , et al. May 21, 1 | 1996-05-21 |
Translating instruction pointer virtual addresses to physical addresses for accessing an instruction cache
Grant 5,500,948 - Hinton , et al. March 19, 1 | 1996-03-19 |
Idiom recognizer within a register alias table
Grant 5,471,633 - Colwell , et al. November 28, 1 | 1995-11-28 |
Mechanism to protect data saved on a local register cache during inter-subsystem calls and returns
Grant 5,448,707 - Hinton , et al. September 5, 1 | 1995-09-05 |
Method and apparatus for preventing incorrect fetching of an instruction of a self-modifying code sequence with dependency on a bufered store
Grant 5,434,987 - Abramson , et al. July 18, 1 | 1995-07-18 |
Instruction fetch unit with early instruction fetch mechanism
Grant 5,423,014 - Hinton , et al. June 6, 1 | 1995-06-06 |
Apparatus and method for maintaining processing consistency in a computer system having multiple processors
Grant 5,420,991 - Konigsfeld , et al. May 30, 1 | 1995-05-30 |
Guess mechanism for faster address calculation in a pipelined microprocessor
Grant 5,335,333 - Hinton , et al. August 2, 1 | 1994-08-02 |
Microprocessor in which multiple instructions are executed in one clock cycle by providing separate machine bus access to a register file for different types of instructions
Grant H1,291 - Hinton , et al. February 1, 1 | 1994-02-01 |
System for executing different cycle instructions by selectively bypassing scoreboard register and canceling the execution of conditionally issued instruction if needed resources are busy
Grant 5,185,872 - Arnold , et al. February 9, 1 | 1993-02-09 |
Six-way access ported RAM array cell
Grant 5,023,844 - Arnold , et al. June 11, 1 | 1991-06-11 |
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