Hineman; Max F.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Hineman; Max F..The latest application filed is for "memory array with shorting structure on a dummy array thereof, and method of providing same".

Company Profile

0.33.34

Hineman; Max F. - Boise ID
Hineman; Max F. - Sunnyvale CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Memory Array With Shorting Structure On A Dummy Array Thereof, And Method Of Providing Same App 20210407582 - Patel; Jaydip Bharatkumar ; et al.	2021-12-30
Memory array with shorting structure on a dummy array thereof, and method of providing same Grant 11,195,575 - Patel , et al. December 7, 2	2021-12-07
Phase-change memory cell implant for dummy array leakage reduction Grant 9,837,604 - Liu , et al. December 5, 2	2017-12-05
Phase-change Memory Cell Implant For Dummy Array Leakage Reduction App 20170125671 - Liu; Lequn J. ; et al.	2017-05-04
Electrode configurations to increase electro-thermal isolation of phase-change memory elements and associated techniques Grant 9,608,042 - Pellizzer , et al. March 28, 2	2017-03-28
Phase-change memory cell implant for dummy array leakage reduction Grant 9,559,146 - Liu , et al. January 31, 2	2017-01-31
Array Of Memory Cells, Methods Associated With Forming Memory Cells That Comprise Programmable Material, And Methods Associated With Forming Memory Cells That Comprise Selector Device Material App 20160307963 - Hineman; Max F. ; et al.	2016-10-20
Electrode Configurations To Increase Electro-thermal Isolation Of Phase-change Memory Elements And Associated Techniques App 20160233271 - Pellizzer; Fabio ; et al.	2016-08-11
Phase-change Memory Cell Implant For Dummy Array Leakage Reduction App 20160181324 - Liu; Lequn J. ; et al.	2016-06-23
Electrode configurations to increase electro-thermal isolation of phase-change memory elements and associated techniques Grant 9,299,747 - Pellizzer , et al. March 29, 2	2016-03-29
Thermal-disturb mitigation in dual-deck cross-point memories Grant 9,231,202 - Pangal , et al. January 5, 2	2016-01-05
Use of etch process post wordline definition to improve data retention in a flash memory device Grant 9,082,714 - Koval , et al. July 14, 2	2015-07-14
Thermal-disturb Mitigation In Dual-deck Cross-point Memories App 20140374686 - Pangal; Kiran ; et al.	2014-12-25
Method to reduce charge buildup during high aspect ratio contact etch Grant 8,673,787 - Sandhu , et al. March 18, 2	2014-03-18
Use Of Etch Process Post Wordline Definition To Improve Data Retention In A Flash Memory Device App 20130264628 - Koval; Randy J. ; et al.	2013-10-10
Method to Reduce Charge Buildup During High Aspect Ratio Contact Etch App 20110250759 - Sandhu; Gurtej S. ; et al.	2011-10-13
Method to reduce charge buildup during high aspect ratio contact etch Grant 7,985,692 - Sandhu , et al. July 26, 2	2011-07-26
Plasma etching methods and contact opening forming methods Grant 7,615,164 - Howard , et al. November 10, 2	2009-11-10
Method To Reduce Charge Buildup During High Aspect Ratio Contact Etch App 20080128389 - Sandhu; Gurtej S. ; et al.	2008-06-05
Method to reduce charge buildup during high aspect ratio contact etch Grant 7,344,975 - Sandhu , et al. March 18, 2	2008-03-18
Methods for forming a metallic damascene structure Grant 7,319,071 - Hineman , et al. January 15, 2	2008-01-15
Plasma reaction chamber liner consisting essentially of osmium Grant 7,293,526 - Hineman , et al. November 13, 2	2007-11-13
Method of forming contact openings Grant 7,255,803 - Howard , et al. August 14, 2	2007-08-14
Plasma reaction chamber assemblies App 20070113975 - Hineman; Max F. ; et al.	2007-05-24
Method to reduce charge buildup during high aspect ratio contact etch App 20070049018 - Sandhu; Gurtej S. ; et al.	2007-03-01
Methods for forming conductive vias in a substrate and electronic devices and systems including an at least partially reversed oxidation injury at an interface between a conductive via and a conductive interconnect structure App 20070007657 - Hineman; Max F. ; et al.	2007-01-11
Method of forming contact openings App 20060255011 - Howard; Bradley J. ; et al.	2006-11-16
Cleaning composition useful in semiconductor integrated circuit fabrication Grant 7,135,444 - Yates , et al. November 14, 2	2006-11-14
Plasma reaction chamber liner comprising ruthenium Grant 7,131,391 - Hineman , et al. November 7, 2	2006-11-07
Methods of etching silicon-oxide-containing compositions Grant 7,118,683 - Hineman , et al. October 10, 2	2006-10-10
Cleaning composition useful in semiconductor integrated circuit fabrication Grant 7,087,561 - Yates , et al. August 8, 2	2006-08-08
Processing method of forming MRAM circuitry Grant 7,067,429 - Li , et al. June 27, 2	2006-06-27
Cleaning composition useful in semiconductor integrated circuit fabricating Grant 7,067,465 - Yates , et al. June 27, 2	2006-06-27
Cleaning composition useful in semiconductor integrated circuit fabrication Grant 7,067,466 - Yates , et al. June 27, 2	2006-06-27
Method of removing etch residues App 20060128159 - Hillyer; Larry ; et al.	2006-06-15
Plasma etching methods and contact opening forming methods App 20050284843 - Howard, Bradley J. ; et al.	2005-12-29
Methods of etching silicon-oxide-containing materials Grant 6,953,531 - Hineman , et al. October 11, 2	2005-10-11
Methods for improving metal-to-metal contact in a via, devices made according to the methods, and systems including the same App 20050170642 - Hineman, Max F. ; et al.	2005-08-04
Methods of enhancing selectivity of etching silicon dioxide relative to one or more organic substances; and plasma reaction chambers App 20050101150 - Hineman, Max F. ; et al.	2005-05-12
Methods of providing an interlevel dielectric layer intermediate different elevation conductive metal layers in the fabrication of integrated circuitry Grant 6,844,255 - McDaniel , et al. January 18, 2	2005-01-18
Cleaning composition useful in semiconductor integrated circuit fabrication Grant 6,831,047 - Yates , et al. December 14, 2	2004-12-14
Methods of forming integrated circuitry, semiconductor processing methods, and processing method of forming MRAM circuitry Grant 6,797,628 - Li , et al. September 28, 2	2004-09-28
Method of removing etch residues App 20040157462 - Hillyer, Larry ; et al.	2004-08-12
Processing method of forming MRAM circuitry App 20040106271 - Li, Li ; et al.	2004-06-03
Method for forming a silicide gate stack for use in a self-aligned contact etch Grant 6,638,843 - Hineman October 28, 2	2003-10-28
Methods of forming integrated circuitry, semiconductor processing methods, and processing method of forming MRAM circuitry App 20030134513 - Li, Li ; et al.	2003-07-17
Methods Of Providing An Interlevel Dielectric Layer Intermediate Different Elevation Conductive Metal Layers In The Fabrication Of Integrated Circuitry App 20030068879 - McDaniel, Terrence ; et al.	2003-04-10
Methods of etching silicon-oxide-containing compositions App 20030024896 - Hineman, Max F. ; et al.	2003-02-06
Plasma reaction chamber assemblies App 20030019842 - Hineman, Max F. ; et al.	2003-01-30
Methods of etching silicon-oxide-containing compositions App 20030019834 - Hineman, Max F. ; et al.	2003-01-30
Cleaning composition useful in semiconductor integrated circuit fabrication App 20020187906 - Yates, Donald L. ; et al.	2002-12-12
Cleaning composition useful in semiconductor integrated circuit fabrication Grant 6,486,108 - Yates , et al. November 26, 2	2002-11-26
Cleaning composition useful in semiconductor integrated circuit fabrication App 20020169089 - Yates, Donald L. ; et al.	2002-11-14
Cleaning composition useful in semiconductor integrated circuit fabrication App 20020165106 - Yates, Donald L. ; et al.	2002-11-07
Cleaning composition useful in semiconductor integrated circuit fabrication App 20020165107 - Yates, Donald L. ; et al.	2002-11-07
Cleaning composition useful in semiconductor integrated circuit fabricating App 20020165105 - Yates, Donald L. ; et al.	2002-11-07
Method for forming a silicide gate stack for use in a self-aligned contact etch App 20020160595 - Hineman, Max F.	2002-10-31
Self-aligned, magnetoresitive random-access memory (MRAM) structure utilizing a spacer containment scheme App 20020105035 - Sandhu, Gurtej ; et al.	2002-08-08
Method for selective etching of oxides Grant 6,372,657 - Hineman , et al. April 16, 2	2002-04-16
Self-aligned, magnetoresistive random-access memory (MRAM) structure utilizing a spacer containment scheme Grant 6,358,756 - Sandhu , et al. March 19, 2	2002-03-19
Methods of providing an interlevel dielectric layer intermediate different elevation conductive metal layers in the fabrication of integrated circuitry Grant 6,350,679 - McDaniel , et al. February 26, 2	2002-02-26
Method for forming a silicide gate stack for use in a self-aligned contact etch App 20010053595 - Hineman, Max F.	2001-12-20
Intracavity laser spectroscope for high sensitivity detection of contaminants Grant 5,689,334 - Atkinson , et al. November 18, 1	1997-11-18

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