Hillman; Daniel

Patent Applications and Registrations

Patent applications and USPTO patent grants for Hillman; Daniel.The latest application filed is for "memory instruction pipeline with a pre-read stage for a write operation for reducing power consumption in a memory device that uses dynamic redundancy registers".

Company Profile

0.9.9

Hillman; Daniel - San Jose CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Memory device with a plurality of memory banks where each memory bank is associated with a corresponding memory instruction pipeline and a dynamic redundancy register Grant 10,628,316 - Berger , et al.	2020-04-21
Memory device with a dual Y-multiplexer structure for performing two simultaneous operations on the same row of a memory bank Grant 10,460,781 - Berger , et al. Oc	2019-10-29
Memory instruction pipeline with a pre-read stage for a write operation for reducing power consumption in a memory device that uses dynamic redundancy registers Grant 10,446,210 - Berger , et al. Oc	2019-10-15
Method of flushing the contents of a dynamic redundancy register to a secure storage area during a power down in a memory device Grant 10,437,723 - Berger , et al. O	2019-10-08
Method of processing incomplete memory operations in a memory device during a power up sequence and a power down sequence using a dynamic redundancy register Grant 10,437,491 - Berger , et al. O	2019-10-08
Method of writing contents in memory during a power up sequence using a dynamic redundancy register in a memory device Grant 10,360,964 - Berger , et al.	2019-07-23
Memory instruction pipeline with an additional write stage in a memory device that uses dynamic redundancy registers Grant 10,192,601 - Berger , et al. Ja	2019-01-29
Smart cache design to prevent overflow for a memory device with a dynamic redundancy register Grant 10,192,602 - Berger , et al. Ja	2019-01-29
Memory Device With A Dual Y-multiplexer Structure For Performing Two Simultaneous Operations On The Same Row Of A Memory Bank App 20180122446 - BERGER; Neal ; et al.	2018-05-03
Method Of Processing Incompleted Memory Operations In A Memory Device During A Power Up Sequence And A Power Down Sequence Using A Dynamic Redundancy Register App 20180121117 - BERGER; Neal ; et al.	2018-05-03
Memory Device With A Plurality Of Memory Banks Where Each Memory Bank Is Associated With A Corresponding Memory Instruction Pipeline And A Dynamic Redundancy Register App 20180121361 - BERGER; Neal ; et al.	2018-05-03
Memory Instruction Pipeline With An Additional Write Stage In A Memory Device That Uses Dynamic Redundancy Registers App 20180122449 - BERGER; Neal ; et al.	2018-05-03
Method Of Writing Contents In Memory During A Power Up Sequence Using A Dynamic Redundancy Register In A Memory Device App 20180122447 - BERGER; Neal ; et al.	2018-05-03
Memory Instruction Pipeline With A Pre-read Stage For A Write Operation For Reducing Power Consumption In A Memory Device That Uses Dynamic Redundancy Registers App 20180122448 - BERGER; Neal ; et al.	2018-05-03
Smart Cache Design To Prevent Overflow For A Memory Device With A Dynamic Redundancy Register App 20180122450 - BERGER; Neal ; et al.	2018-05-03
Method Of Flushing The Contents Of A Dynamic Redundancy Register To A Secure Storage Area During A Power Down In A Memory Device App 20180121355 - BERGER; Neal ; et al.	2018-05-03
Circuit and method for glitch correction Grant 7,541,880 - Galloway , et al. June 2, 2	2009-06-02
Circuit And Method For Glitch Correction App 20080258835 - GALLOWAY; Brian Jeffrey ; et al.	2008-10-23

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