HILL; Ervin T.

Patent Applications and Registrations

Patent applications and USPTO patent grants for HILL; Ervin T..The latest application filed is for "dielectric barrier at non-volatile memory tile edge".

Company Profile

9.8.9

HILL; Ervin T. - Boise ID
Hill; Ervin T. - Los Lunas NM

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Dielectric Barrier At Non-volatile Memory Tile Edge App 20210296582 - BAKER; Kevin L. ; et al.	2021-09-23
Dielectric barrier at non-volatile memory tile edge Grant 11,069,855 - Baker , et al. July 20, 2	2021-07-20
Dielectric Barrier At Non-volatile Memory Tile Edge App 20210005810 - BAKER; Kevin L. ; et al.	2021-01-07
Non-contact measurement of memory cell threshold voltage Grant 10,672,500 - Majumdar , et al.	2020-06-02
Non-contact electron beam probing techniques and related structures Grant 10,650,891 - Majumdar , et al.	2020-05-12
Non-contact Electron Beam Probing Techniques And Related Structures App 20190355418 - Majumdar; Amitava ; et al.	2019-11-21
Non-contact Measurement Of Memory Cell Threshold Voltage App 20190341122 - Majumdar; Amitava ; et al.	2019-11-07
Non-contact electron beam probing techniques and related structures Grant 10,403,359 - Majumdar , et al. Sep	2019-09-03
Non-contact measurement of memory cell threshold voltage Grant 10,381,101 - Majumdar , et al. A	2019-08-13
Non-contact Electron Beam Probing Techniques And Related Structures App 20190189209 - Majumdar; Amitava ; et al.	2019-06-20
Non-contact Measurement Of Memory Cell Threshold Voltage App 20190189237 - Majumdar; Amitava ; et al.	2019-06-20
Methods of semiconductor processing involving forming doped polysilicon on undoped polysilicon Grant 7,943,463 - Khandekar , et al. May 17, 2	2011-05-17
Methods Of Semiconductor Processing Involving Forming Doped Polysilicon On Undoped Polysilicon App 20100255664 - Khandekar; Anish ; et al.	2010-10-07
Method for manufacturing high density flash memory and high performance logic on a single die Grant 7,186,614 - Chao , et al. March 6, 2	2007-03-06
Method and apparatus for self-aligned MOS patterning Grant 7,153,780 - Hill , et al. December 26, 2	2006-12-26
Method and apparatus for self-aligned MOS patterning App 20050215039 - Hill, Ervin T. ; et al.	2005-09-29
Method for manufacturing high density flash memory and high performance logic on a single die App 20050098821 - Chao, Henry S. ; et al.	2005-05-12

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