Hieter; Nathaniel D.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Hieter; Nathaniel D..The latest application filed is for "leverage cycle stealing within optimization flows".

Company Profile

7.13.13

Hieter; Nathaniel D. - Clinton Corners NY
Hieter; Nathaniel D. - Hopewell Junction NY

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Leverage cycle stealing within optimization flows Grant 10,970,447 - Hieter , et al. April 6, 2	2021-04-06
Leverage cycle stealing within optimization flows Grant 10,552,562 - Hieter , et al. Fe	2020-02-04
Leverage cycle stealing within optimization flows Grant 10,540,465 - Hieter , et al. Ja	2020-01-21
Leverage Cycle Stealing Within Optimization Flows App 20190286773 - Hieter; Nathaniel D. ; et al.	2019-09-19
Leverage Cycle Stealing Within Optimization Flows App 20190220561 - Hieter; Nathaniel D. ; et al.	2019-07-18
Leverage cycle stealing within optimization flows Grant 10,216,875 - Hieter , et al. Feb	2019-02-26
Optimizing placement of circuit resources using a globally accessible placement memory Grant 10,210,297 - Hathaway , et al. Feb	2019-02-19
Leverage Cycle Stealing Within Optimization Flows App 20180239843 - Hieter; Nathaniel D. ; et al.	2018-08-23
Leverage Cycle Stealing Within Optimization Flows App 20180239845 - Hieter; Nathaniel D. ; et al.	2018-08-23
Leverage Cycle Stealing Within Optimization Flows App 20180239844 - Hieter; Nathaniel D. ; et al.	2018-08-23
Optimizing placement of circuit resources using a globally accessible placement memory Grant 9,747,400 - Hathaway , et al. August 29, 2	2017-08-29
Optimizing placement of circuit resources using a globally accessible placement memory Grant 9,703,914 - Hathaway , et al. July 11, 2	2017-07-11
Managing virtual boundaries to enable lock-free concurrent region optimization of an integrated circuit Grant 9,639,654 - Chen , et al. May 2, 2	2017-05-02
Optimizing Placement Of Circuit Resources Using A Globally Accessible Placement Memory App 20170083642 - Hathaway; David J. ; et al.	2017-03-23
Optimizing Placement Of Circuit Resources Using A Globally Accessible Placement Memory App 20170083641 - Hathaway; David J. ; et al.	2017-03-23
Optimizing Placement Of Circuit Resources Using A Globally Accessible Placement Memory App 20160300006 - Hathaway; David J. ; et al.	2016-10-13
Optimizing Placement Of Circuit Resources Using A Globally Accessible Placement Memory App 20160283633 - Hathaway; David J. ; et al.	2016-09-29
Optimizing placement of circuit resources using a globally accessible placement memory Grant 9,436,791 - Hathaway , et al. September 6, 2	2016-09-06
Optimizing placement of circuit resources using a globally accessible placement memory Grant 9,418,188 - Hathaway , et al. August 16, 2	2016-08-16
Managing Virtual Boundaries To Enable Lock-free Concurrent Region Optimization Of An Integrated Circuit App 20160171147 - CHEN; BIJIAN ; et al.	2016-06-16
Method for enabling multiple incompatible or costly timing environment for efficient timing closure Grant 8,302,049 - Musante , et al. October 30, 2	2012-10-30
Cone-aware spare cell placement using hypergraph connectivity analysis Grant 8,234,612 - Goodman , et al. July 31, 2	2012-07-31
Method for Enabling Multiple Incompatible or Costly Timing Environments for Efficient Timing Closure App 20120144357 - Musante; Frank J. ; et al.	2012-06-07
Cone-aware Spare Cell Placement Using Hypergraph Connectivity Analysis App 20120054707 - Goodman; Benjiman L. ; et al.	2012-03-01
Influence-based circuit design Grant 7,500,207 - Bhattacharya , et al. March 3, 2	2009-03-03
Influence-based circuit design App 20070192752 - Bhattacharya; Subhrajit ; et al.	2007-08-16

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