| Patent | Date |
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Methods and systems for optimized translation of a virtual address having multiple virtual address portions using multiple translation lookaside buffer (TLB) arrays for variable page sizes
Grant 11,409,663 - Campbell , et al. August 9, 2 | 2022-08-09 |
Methods and systems for incorporating non-tree based address translation into a hierarchical translation lookaside buffer (TLB)
Grant 11,221,963 - Campbell , et al. January 11, 2 | 2022-01-11 |
Operation of a multi-slice processor implementing a unified page walk cache
Grant 11,157,415 - Hicks , et al. October 26, 2 | 2021-10-26 |
Virtual cache mechanism for program break point register exception handling
Grant 11,061,810 - Campbell , et al. July 13, 2 | 2021-07-13 |
Methods And Systems For Optimized Translation Of A Virtual Address Having Multiple Virtual Address Portions Using Multiple Translation Lookaside Buffer (tlb) Arrays For Variable Page Sizes
App 20210049107 - Campbell; David ; et al. | 2021-02-18 |
Methods and systems for optimized translation of a virtual address having multiple virtual address portions using multiple translation lookaside buffer (TLB) arrays for variable page sizes
Grant 10,915,459 - Campbell , et al. February 9, 2 | 2021-02-09 |
Operation of a multi-slice processor implementing exception handling in a nested translation environment
Grant 10,824,494 - Hicks , et al. November 3, 2 | 2020-11-03 |
Virtual Cache Mechanism for Program Break Point Register Exception Handling
App 20200272557 - Campbell; David ; et al. | 2020-08-27 |
Methods and systems for predicting virtual address
Grant 10,740,248 - Campbell , et al. A | 2020-08-11 |
Methods and Systems for Predicting Virtual Address
App 20200192817 - Campbell; David ; et al. | 2020-06-18 |
Methods and Systems for Incorporating Non-Tree Based Address Translation Into a Hierarchical Translation Lookaside Buffer (TLB)
App 20200183858 - Campbell; David ; et al. | 2020-06-11 |
Performance Optimized Congruence Class Matching For Multiple Concurrent Radix Translations
App 20200174793 - Campbell; David ; et al. | 2020-06-04 |
Performance optimized congruence class matching for multiple concurrent radix translations
Grant 10,649,778 - Campbell , et al. | 2020-05-12 |
Methods And Systems For Optimized Translation Lookaside Buffer (tlb) Lookups For Variable Page Sizes
App 20200133881 - Campbell; David ; et al. | 2020-04-30 |
Operation Of A Multi-slice Processor Implementing A Unified Page Walk Cache
App 20200125496 - HICKS; DWAIN A. ; et al. | 2020-04-23 |
Methods and systems for incorporating non-tree based address translation into a hierarchical translation lookaside buffer (TLB)
Grant 10,621,106 - Campbell , et al. | 2020-04-14 |
Operation of a multi-slice processor implementing a unified page walk cache
Grant 10,534,715 - Hicks , et al. Ja | 2020-01-14 |
Operation Of A Multi-slice Processor Implementing Exception Handling In A Nested Translation Environment
App 20180293126 - HICKS; DWAIN A. ; et al. | 2018-10-11 |
Operation of a multi-slice processor implementing exception handling in a nested translation environment
Grant 10,042,691 - Hicks , et al. August 7, 2 | 2018-08-07 |
Operation Of A Multi-slice Processor Implementing Exception Handling In A Nested Translation Environment
App 20170308425 - HICKS; DWAIN A. ; et al. | 2017-10-26 |
Operation Of A Multi-slice Processor Implementing A Unified Page Walk Cache
App 20170308474 - HICKS; DWAIN A. ; et al. | 2017-10-26 |
Systems for executing load instructions that achieve sequential load consistency
Grant 7,730,290 - Barrick , et al. June 1, 2 | 2010-06-01 |
Systems For Executing Load Instructions That Achieve Sequential Load Consistency
App 20080148017 - Barrick; Brian David ; et al. | 2008-06-19 |
Method and systems for executing load instructions that achieve sequential load consistency
Grant 7,376,816 - Barrick , et al. May 20, 2 | 2008-05-20 |
Systems and methods for executing load instructions that avoid order violations
Grant 7,302,527 - Barrick , et al. November 27, 2 | 2007-11-27 |
Systems and methods for executing load instructions that avoid order violations
App 20060107021 - Barrick; Brian David ; et al. | 2006-05-18 |
Method and systems for executing load instructions that achieve sequential load consistency
App 20060106985 - Barrick; Brian David ; et al. | 2006-05-18 |
System for controlling access to external cache memories of differing size
Grant 6,604,173 - Cheong , et al. August 5, 2 | 2003-08-05 |
Shared L2 support for inclusion property in split L1 data and instruction caches
Grant 5,694,573 - Cheong , et al. December 2, 1 | 1997-12-02 |
Hierarchical cache arrangement wherein the replacement of an LRU entry in a second level cache is prevented when the cache entry is the only inclusive entry in the first level cache
Grant 5,584,013 - Cheong , et al. December 10, 1 | 1996-12-10 |
Multiprocessor system with shared cache and data input/output circuitry for transferring data amount greater than system bus capacity
Grant 5,581,734 - DiBrino , et al. December 3, 1 | 1996-12-03 |
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