Hibbeler; Jason D.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Hibbeler; Jason D..The latest application filed is for "optimizing integrated circuit designs based on interactions between multiple integration design rules".

Company Profile

4.63.64

Hibbeler; Jason D. - Hinesburg VT
Hibbeler; Jason D. - Williston VT
Hibbeler; Jason D - Essex Junction VT
Hibbeler; Jason D. - Essex Junction VT US

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Optimizing integrated circuit designs based on interactions between multiple integration design rules Grant 10,628,544 - Chidambarrao , et al.	2020-04-21
Optimizing integrated circuit designs based on interactions between multiple integration design rules Grant 10,592,627 - Chidambarrao , et al.	2020-03-17
Optimizing Integrated Circuit Designs Based On Interactions Between Multiple Integration Design Rules App 20190095550 - Chidambarrao; Dureseti ; et al.	2019-03-28
Optimizing Integrated Circuit Designs Based On Interactions Between Multiple Integration Design Rules App 20190095551 - Chidambarrao; Dureseti ; et al.	2019-03-28
Integrated circuit design layout optimizer based on process variation and failure mechanism Grant 10,083,272 - Clevenger , et al. September 25, 2	2018-09-25
Integrated Circuit Design Layout Optimizer Based On Process Variation And Failure Mechanism App 20180046746 - Clevenger; Lawrence A. ; et al.	2018-02-15
Immunity to inline charging damage in circuit designs Grant 9,741,707 - Henderson , et al. August 22, 2	2017-08-22
Immunity to inline charging damage in circuit designs Grant 9,741,706 - Henderson , et al. August 22, 2	2017-08-22
Method for conversion of commercial microprocessor to radiation-hardened processor and resulting processor Grant 9,646,125 - Fifield , et al. May 9, 2	2017-05-09
Tunable sector buffer for wide bandwidth resonant global clock distribution Grant 9,612,612 - Bucelot , et al. April 4, 2	2017-04-04
Immunity To Inline Charging Damage In Circuit Designs App 20160328513 - Henderson; Zachary ; et al.	2016-11-10
Immunity To Inline Charging Damage In Circuit Designs App 20160329317 - Henderson; Zachary ; et al.	2016-11-10
Immunity to inline charging damage in circuit designs Grant 9,378,329 - Henderson , et al. June 28, 2	2016-06-28
Setting switch size and transition pattern in a resonant clock distribution system Grant 9,268,886 - Hibbeler , et al. February 23, 2	2016-02-23
Tunable Sector Buffer for Wide Bandwidth Resonant Global Clock Distribution App 20150234422 - Bucelot; Thomas J. ; et al.	2015-08-20
Tunable sector buffer for wide bandwidth resonant global clock distribution Grant 9,058,130 - Bucelot , et al. June 16, 2	2015-06-16
Wide bandwidth resonant global clock distribution Grant 9,054,682 - Bucelot , et al. June 9, 2	2015-06-09
Setting switch size and transition pattern in a resonant clock distribution system Grant 8,887,118 - Hibbeler , et al. November 11, 2	2014-11-11
Setting switch size and transition pattern in a resonant clock distribution system Grant 8,850,373 - Hibbeler , et al. September 30, 2	2014-09-30
Method For Conversion Of Commercial Microprocessor To Radiation-hardened Processor And Resulting Processor App 20140258958 - FIFIELD; John A. ; et al.	2014-09-11
Setting Switch Size And Transition Pattern In A Resonant Clock Distribution System App 20140245250 - HIBBELER; Jason D. ; et al.	2014-08-28
Setting Switch Size And Transition Pattern In A Resonant Clock Distribution System App 20140245244 - HIBBELER; Jason D. ; et al.	2014-08-28
Setting Switch Size And Transition Pattern In A Resonant Clock Distribution System App 20140240021 - HIBBELER; Jason D. ; et al.	2014-08-28
Tunable Sector Buffer for Wide Bandwidth Resonant Global Clock Distribution App 20140223210 - Bucelot; Thomas J. ; et al.	2014-08-07
Wide Bandwidth Resonant Global Clock Distribution App 20140218087 - Bucelot; Thomas J. ; et al.	2014-08-07
Changing Resonant Clock Modes App 20140167832 - Bucelot; Thomas J. ; et al.	2014-06-19
Changing resonant clock modes Grant 8,736,342 - Bucelot , et al. May 27, 2	2014-05-27
Variable resistance switch for wide bandwidth resonant global clock distribution Grant 8,704,576 - Bucelot , et al. April 22, 2	2014-04-22
Technology migration for integrated circuits with radical design restrictions Grant 8,464,189 - Allen , et al. June 11, 2	2013-06-11
Method of distributing a random variable using statistically correct spatial interpolation continuously with spatially inhomogeneous statistical correlation versus distance, standard deviation, and mean Grant 8,423,328 - Cohn , et al. April 16, 2	2013-04-16
Method for computing the sensitivity of a VLSI design to both random and systematic defects using a critical area analysis tool Grant 8,418,090 - Bickford , et al. April 9, 2	2013-04-09
Image sensor pixel structure employing a shared floating diffusion Grant 8,405,751 - Hibbeler , et al. March 26, 2	2013-03-26
Redundant micro-loop structure for use in an integrated circuit physical design process and method of forming the same Grant 8,234,594 - Anderson , et al. July 31, 2	2012-07-31
Method for IC wiring yield optimization, including wire widening during and after routing Grant 8,230,378 - Cohn , et al. July 24, 2	2012-07-24
Method For Computing The Sensitivity Of A Vlsi Design To Both Random And Systematic Defects Using A Critical Area Analysis Tool App 20120137262 - Bickford; Jeanne P. ; et al.	2012-05-31
Automated sensitivity definition and calibration for design for manufacturing tools Grant 8,141,027 - Culp , et al. March 20, 2	2012-03-20
Apparatus and computer program product for semiconductor yield estimation Grant 8,136,066 - Bickford , et al. March 13, 2	2012-03-13
Method for computing the sensitivity of a VLSI design to both random and systematic defects using a critical area analysis tool Grant 8,132,129 - Bickford , et al. March 6, 2	2012-03-06
Test yield estimate for semiconductor products created from a library Grant 8,010,916 - Bickford , et al. August 30, 2	2011-08-30
Design structure for a redundant micro-loop structure for use in an integrated circuit physical design process and method of forming the same Grant 7,984,394 - Anderson , et al. July 19, 2	2011-07-19
Automated Sensitivity Definition And Calibration For Design For Manufacturing Tools App 20110166686 - Culp; James A. ; et al.	2011-07-07
Redundant micro-loop structure for use in an integrated circuit physical design process and method of forming the same Grant 7,960,836 - Anderson , et al. June 14, 2	2011-06-14
Method For Conversion Of Commercial Microprocessor To Radiation-hardened Processor And Resulting Processor App 20110088008 - FIFIELD; John A. ; et al.	2011-04-14
Method of Distributing a Random Variable Using Statistically Correct Spatial Interpolation Continuously With Spatially Inhomogeneous Statistical Correlation Versus Distance, Standard Deviation, and Mean App 20110077916 - Cohn; John M ; et al.	2011-03-31
Image Sensor Pixel Structure Employing A Shared Floating Diffusion App 20110025892 - Hibbeler; Jason D. ; et al.	2011-02-03
Integrated circuit selective scaling Grant 7,882,463 - Heng , et al. February 1, 2	2011-02-01
Layout optimization using parameterized cells Grant 7,865,848 - Gernhoefer , et al. January 4, 2	2011-01-04
Design Structure for a Redundant Micro-Loop Structure for use in an Integrated Circuit Physical Design Process and Method of Forming the Same App 20100211923 - Anderson; Brent A. ; et al.	2010-08-19
Technology Migration For Integrated Circuits With Radical Design Restrictions App 20100185997 - Allen; Robert J. ; et al.	2010-07-22
Technology migration for integrated circuits with radical design restrictions Grant 7,761,821 - Allen , et al. July 20, 2	2010-07-20
Method, apparatus, and computer program product for displaying and modifying the critical area of an integrated circuit design Grant 7,752,589 - Allen , et al. July 6, 2	2010-07-06
Method and system for analyzing an integrated circuit based on sample windows selected using an open deterministic sequencing technique Grant 7,752,580 - Braasch , et al. July 6, 2	2010-07-06
Context aware sub-circuit layout modification Grant 7,735,042 - Gray , et al. June 8, 2	2010-06-08
Systematic yield in semiconductor manufacture Grant 7,725,864 - Bergeron , et al. May 25, 2	2010-05-25
Systematic yield in semiconductor manufacture Grant 7,721,240 - Bergeron , et al. May 18, 2	2010-05-18
Content based yield prediction of VLSI designs Grant 7,661,081 - Allen , et al. February 9, 2	2010-02-09
Method for IC wiring yield optimization, including wire widening during and after routing Grant 7,657,859 - Cohn , et al. February 2, 2	2010-02-02
Method For Ic Wiring Yield Optimization, Including Wire Widening During And After Routing App 20100023913 - Cohn; John M. ; et al.	2010-01-28
Technology migration for integrated circuits with radical design restrictions Grant 7,610,565 - Allen , et al. October 27, 2	2009-10-27
Independent migration of hierarchical designs with methods of finding and fixing opens during migration Grant 7,568,173 - Gernhoefer , et al. July 28, 2	2009-07-28
Design Structure for a Redundant Micro-Loop Structure for use in an Integrated Circuit Physical Design Process and Method of Forming the Same App 20090158231 - Anderson; Brent A. ; et al.	2009-06-18
Apparatus And Computer Program Product For Semiconductor Yield Estimation App 20090113364 - Bickford; Jeanne Paulette Spence ; et al.	2009-04-30
Method For Computing The Sensistivity Of A Vlsi Design To Both Random And Systematic Defects Using A Critical Area Analysis Tool App 20090113360 - BICKFORD; JEANNE P. ; et al.	2009-04-30
Layout Optimization Using Parameterized Cells App 20090064061 - Gernhoefer; Veit ; et al.	2009-03-05
Semiconductor yield estimation Grant 7,496,874 - Bickford , et al. February 24, 2	2009-02-24
Method for implementing overlay-based modification of VLSI design layout Grant 7,490,308 - Gonzalez , et al. February 10, 2	2009-02-10
Context Aware Sub-circuit Layout Modification App 20090037851 - Gray; Michael S. ; et al.	2009-02-05
Polygonal Area Design Rule Correction Method For Vlsi Layouts App 20090037850 - Gray; Michael S. ; et al.	2009-02-05
Method for computing the sensitivity of a VLSI design to both random and systematic defects using a critical area analysis tool Grant 7,487,476 - Bickford , et al. February 3, 2	2009-02-03
Method And System For Analyzing An Integrated Circuit Based On Sample Windows Selected Using An Open Deterministic Sequencing Technique App 20090031263 - Braasch; Sarah C. ; et al.	2009-01-29
Minimum layout perturbation-based artwork legalization with grid constraints for hierarchical designs Grant 7,484,197 - Allen , et al. January 27, 2	2009-01-27
Independent Migration Of Hierarchical Designs With Methods Of Finding And Fixing Opens During Migration App 20080313581 - Gernhoefer; Veit ; et al.	2008-12-18
Method, apparatus and computer program product for optimizing an integrated circuit layout Grant 7,454,721 - Hibbeler , et al. November 18, 2	2008-11-18
Content Based Yield Prediction Of Vlsi Designs App 20080195989 - Allen; Robert J. ; et al.	2008-08-14
Test Yield Estimate For Semiconductor Products Created From A Library App 20080189664 - Bickford; Jeanne ; et al.	2008-08-07
Method Of Optimizing Hierarchical Very Large Scale Integration (vlsi) Design By Use Of Cluster-based Logic Cell Cloning App 20080172638 - Gray; Michael S. ; et al.	2008-07-17
Method, Apparatus, And Computer Program Product For Displaying And Modifying The Critical Area Of An Integrated Circuit Design. App 20080168414 - Allen; Robert J. ; et al.	2008-07-10
Yield optimization in router for systematic defects Grant 7,398,485 - Bickford , et al. July 8, 2	2008-07-08
Redundant Micro-loop Structure For Use In An Intergrated Circuit Physical Design Process And Method Of Forming The Same App 20080150149 - Anderson; Brent A. ; et al.	2008-06-26
Automated Optimization Of Vlsi Layouts For Regularity App 20080155482 - Chidambarrao; Dureseti ; et al.	2008-06-26
Integrated Circuit Selective Scaling App 20080148210 - Heng; Fook-Luen ; et al.	2008-06-19
Content based yield prediction of VLSI designs Grant 7,389,480 - Allen , et al. June 17, 2	2008-06-17
Test yield estimate for semiconductor products created from a library Grant 7,386,815 - Bickford , et al. June 10, 2	2008-06-10
Systematic Yield In Semiconductor Manufacture App 20080104568 - BERGERON; Paul H. ; et al.	2008-05-01
Redundant Micro-Loop Structure For Use In An Integrated Circuit Physical Design Process And Method Of Forming The Same App 20080097738 - Anderson; Brent A. ; et al.	2008-04-24
Integrated circuit selective scaling Grant 7,363,601 - Heng , et al. April 22, 2	2008-04-22
Systematic Yield In Semiconductor Manufacture App 20080059918 - Bergeron; Paul H. ; et al.	2008-03-06
Systematic yield in semiconductor manufacture Grant 7,337,415 - Bergeron , et al. February 26, 2	2008-02-26
Use of redundant routes to increase the yield and reliability of a VLSI layout Grant 7,308,669 - Buehler , et al. December 11, 2	2007-12-11
Technology Migration For Integrated Circuits With Radical Design Restrictions App 20070277129 - Allen; Robert J. ; et al.	2007-11-29
Technology migration for integrated circuits with radical design restrictions Grant 7,302,651 - Allen , et al. November 27, 2	2007-11-27
Via redundancy based on subnet timing information, target via distant along path from source and/or target via net/subnet characteristic Grant 7,290,226 - Correale, Jr. , et al. October 30, 2	2007-10-30
Minimum Layout Perturbation-based Artwork Legalization With Grid Constraints For Hierarchical Designs App 20070245283 - Allen; RobertJ ; et al.	2007-10-18
Method For Computing The Sensitivity Of A Vlsi Design To Both Random And Systematic Defects Using A Critical Area Analysis Tool App 20070240085 - Bickford; Jeanne P. ; et al.	2007-10-11
Yield Optimization In Router For Systematic Defects App 20070240090 - Bickford; JeanneP ; et al.	2007-10-11
Method For Implementing Overlay-based Modification Of Vlsi Design Layout App 20070234260 - Gonzalez; Christopher J. ; et al.	2007-10-04
Technology Migration For Integrated Circuits With Radical Design Restrictions App 20070198961 - Allen; Robert J. ; et al.	2007-08-23
Integrated circuit yield enhancement using Voronoi diagrams Grant 7,260,790 - Allen , et al. August 21, 2	2007-08-21
Technology migration for integrated circuits with radical design restrictions Grant 7,257,783 - Allen , et al. August 14, 2	2007-08-14
A Method , Apparatus And Computer Program Product For Semiconductor Yield Estimation App 20070143720 - Bickford; Jeanne Paulette Spence ; et al.	2007-06-21
A Method For Ic Wiring Yield Optimization, Including Wire Widening During And After Routing App 20070136714 - Cohn; John M. ; et al.	2007-06-14
Test Yield Estimate For Semiconductor Products Created From A Library App 20070099236 - Bickford; Jeanne ; et al.	2007-05-03
The Use Of Redundant Routes To Increase The Yield And Reliability Of A Vlsi Layout App 20060265684 - Buehler; Markus T. ; et al.	2006-11-23
Content Based Yield Prediction Of Vlsi Designs App 20060253806 - Allen; Robert J. ; et al.	2006-11-09
Cloned and original circuit shape merging Grant 7,120,887 - Bonges, III , et al. October 10, 2	2006-10-10
Via Redundancy Based On Subnet Timing Information, Target Via Distant Along Path From Source And/or Target Via Net/subnet Characteristic App 20060225005 - Correale; Anthony JR. ; et al.	2006-10-05
Dynamic CPU usage profiling and function call tracing Grant 7,093,234 - Hibbeler , et al. August 15, 2	2006-08-15
Integrated Circuit Yield Enhancement Using Voronoi Diagrams App 20060150130 - Allen; Robert J. ; et al.	2006-07-06
Method and system for obtaining a feasible integer solution from a half-integer solution in hierarchical circuit layout optimization Grant 7,062,729 - Gray , et al. June 13, 2	2006-06-13
Technology Migration For Integrated Circuits With Radical Design Restrictions App 20060101357 - Allen; Robert J. ; et al.	2006-05-11
Technology Migration For Integrated Circuits With Radical Design Restrictions App 20060101356 - Allen; Robert J. ; et al.	2006-05-11
Integrated Circuit Selective Scaling App 20060085768 - Heng; Fook-Luen ; et al.	2006-04-20
Improving Systematic Yield In Semiconductor Manufacture App 20060085769 - Bergeron; Paul H. ; et al.	2006-04-20
Method and system for obtaining a feasible integer solution from a half-integer solution in hierarchical circuit layout optimization App 20060064661 - Gray; Michael S. ; et al.	2006-03-23
Automated configuration of on-circuit facilities Grant 6,970,809 - Feng , et al. November 29, 2	2005-11-29
Via Spacing Violation Correction Method, System And Program Product App 20050240884 - Frederick, Terry L. ; et al.	2005-10-27
Use of a layout-optimization tool to increase the yield and reliability of VLSI designs Grant 6,941,528 - Allen , et al. September 6, 2	2005-09-06
Cloned And Original Circuit Shape Merging App 20050160390 - Bonges, Henry A. III ; et al.	2005-07-21
The Use Of A Layout-optimization Tool To Increase The Yield And Reliability Of Vlsi Designs App 20050050500 - Allen, Robert J. ; et al.	2005-03-03
The Use Of A Layout-optimization Tool To Increase The Yield And Reliability Of Vlsi Designs App 20050048677 - Allen, Robert J. ; et al.	2005-03-03
The Use Of A Layout-optimization Tool To Increase The Yield And Reliability Of Vlsi Designs App 20050050501 - Allen, Robert J. ; et al.	2005-03-03
Automated configuration of on-circuit facilities App 20030046616 - Feng, Cheng A. ; et al.	2003-03-06
Dynamic CPU usage profiling and function call tracing App 20030041316 - Hibbeler, Jason D. ; et al.	2003-02-27