Heyne; Patrick

Patent Applications and Registrations

Patent applications and USPTO patent grants for Heyne; Patrick.The latest application filed is for "delay circuit".

Company Profile

0.24.27

Heyne; Patrick - Munich DE
Heyne; Patrick - Munchen DE

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Delay circuit Grant 7,629,820 - Heyne , et al. December 8, 2	2009-12-08
Delay locked loop Grant 7,457,392 - Weis , et al. November 25, 2	2008-11-25
Device and method for the synchronization of clock signals and adjustment of the duty cycle of the clock signal Grant 7,414,445 - Heyne August 19, 2	2008-08-19
Read latency control circuit Grant 7,404,018 - Dietrich , et al. July 22, 2	2008-07-22
Delay locked loop and method for setting a delay chain Grant 7,391,245 - Heyne , et al. June 24, 2	2008-06-24
Method and circuit arrangement for resetting an integrated circuit Grant 7,363,561 - Dietrich , et al. April 22, 2	2008-04-22
Delay Circuit App 20080074159 - Heyne; Patrick ; et al.	2008-03-27
Amplifier Circuit and Method for Correcting the Duty Ratio of a Differential Clock Signal App 20070285139 - Heyne; Patrick	2007-12-13
Device to be used in the synchronization of clock pulses, as well as a clock pulse synchronization process Grant 7,304,515 - Brox , et al. December 4, 2	2007-12-04
Signal delay loop and method for locking a signal delay loop App 20070273416 - Heyne; Patrick	2007-11-29
Device and method for the synchronization of clock signals and adjustment of the duty cycle of the clock signal App 20070182470 - Heyne; Patrick	2007-08-09
Delay locked loop and method for setting a delay chain App 20060273834 - Heyne; Patrick ; et al.	2006-12-07
Integratable, controllable delay device, use of a delay device, as well as an integratable multiplexer for use in a delay device Grant 7,126,401 - Heyne , et al. October 24, 2	2006-10-24
Circuit arrangement for generating a synchronization signal App 20060214709 - Nygren; Aaron ; et al.	2006-09-28
Delay locked loop Grant 7,016,452 - Partsch , et al. March 21, 2	2006-03-21
Read latency control circuit App 20050270852 - Dietrich, Stefan ; et al.	2005-12-08
Integrated synchronous memory and memory configuration having a memory module with at least one synchronous memory Grant 6,967,893 - Heyne November 22, 2	2005-11-22
Method and circuit arrangement for resetting an integrated circuit App 20050253638 - Dietrich, Stefan ; et al.	2005-11-17
Integratable, controllable delay device, use of a delay device, as well as an integratable multiplexer for use in a delay device App 20050218954 - Heyne, Patrick ; et al.	2005-10-06
Device to be used in the synchronization of clock pulses, as well as a clock pulse synchronization process App 20050179478 - Brox, Martin ; et al.	2005-08-18
Synchronous integrated memory Grant 6,928,025 - Hein , et al. August 9, 2	2005-08-09
Method and logic/memory module for correcting the duty cycle of at least one control/reference signal Grant 6,806,752 - Heyne October 19, 2	2004-10-19
Circuit configuration for generating a controllable output voltage Grant 6,784,650 - Hein , et al. August 31, 2	2004-08-31
Optimized-delay multiplexer Grant 6,756,820 - Heyne , et al. June 29, 2	2004-06-29
Integrable, controllable delay device, delay device in a control loop, and method for delaying a clock signal using a delay device Grant 6,737,901 - Hein , et al. May 18, 2	2004-05-18
Integrated synchronous memory and memory configuration having a memory module with at least one synchronous memory App 20040022106 - Heyne, Patrick	2004-02-05
Integrated circuit having a test operating mode and method for testing a multiplicity of such circuits Grant 6,670,802 - Dietrich , et al. December 30, 2	2003-12-30
Delay locked loop for generating complementary clock signals Grant 6,661,265 - Partsch , et al. December 9, 2	2003-12-09
Current mirror circuit Grant 6,657,422 - Heyne , et al. December 2, 2	2003-12-02
Circuit configuration for generating a controllable output voltage App 20030205992 - Hein, Thomas ; et al.	2003-11-06
Method and logic/memory module for correcting the duty cycle of at least one control/reference signal App 20030128061 - Heyne, Patrick	2003-07-10
Semiconductor memory having a delay locked loop Grant 6,584,021 - Heyne , et al. June 24, 2	2003-06-24
Delay locked loop App 20030094984 - Weis, Christian ; et al.	2003-05-22
Integrable, controllable delay device, delay device in a control loop, and method for delaying a clock signal using a delay device App 20030085747 - Hein, Thomas ; et al.	2003-05-08
Delay locked loop App 20030012322 - Partsch, Torsten ; et al.	2003-01-16
Delay locked loop for generating complementary clock signals App 20030001636 - Partsch, Torsten ; et al.	2003-01-02
Circuit configuration for enabling a clock signal in a manner dependent on an enable signal App 20020153924 - Menczigar, Ullrich ; et al.	2002-10-24
Integrated memory having a row access controller for activating and deactivating row lines App 20020141279 - Dietrich, Stefan ; et al.	2002-10-03
Integrated circuit having a test operating mode and method for testing a multiplicity of such circuits App 20020133750 - Dietrich, Stefan ; et al.	2002-09-19
Semiconductor memory having a delay locked loop App 20020093855 - Heyne, Patrick ; et al.	2002-07-18
Current mirror circuit App 20020089319 - Heyne, Patrick ; et al.	2002-07-11
Circuit configuration for programming a delay in a signal path App 20020079925 - Dietrich, Stefan ; et al.	2002-06-27
Voltage pump with switch-on control App 20020075707 - Dietrich, Stefan ; et al.	2002-06-20
Memory component with short access time Grant 6,388,944 - Schrogmeier , et al. May 14, 2	2002-05-14
Integrated circuit with a phase locked loop Grant 6,351,167 - Hein , et al. February 26, 2	2002-02-26
Circuit configuration for compensating runtime and pulse-duty-factor differences between two input signals App 20020021155 - Heyne, Patrick ; et al.	2002-02-21
Memory component with short access time App 20010038566 - Schrogmeier, Peter ; et al.	2001-11-08
Circuit configuration for generating an output clock signal with optimized signal generation time App 20010033523 - Hein, Thomas ; et al.	2001-10-25
Circuit configuration for producing complementary signals Grant 6,198,328 - Heyne , et al. March 6, 2	2001-03-06
Circuit configuration and method for automatic recognition and elimination of word line/bit line short circuits Grant 6,125,066 - Gratz , et al. September 26, 2	2000-09-26
Databus Grant 6,060,908 - Heyne , et al. May 9, 2	2000-05-09

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