Patent applications and USPTO patent grants for Heuristic Physics Laboratories.The latest application filed is for "method for using wafer navigation to reduce testing times of integrated circuit wafers".
Patent | Date |
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Method for using wafer navigation to reduce testing times of integrated circuit wafers Grant 6,154,714 - Lepejian November 28, 2 | 2000-11-28 |
Method for using inspection data for improving throughput of stepper operations in manufacturing of integrated circuits Grant 6,096,093 - Caywood , et al. August 1, 2 | 2000-08-01 |
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