Hetherington; Ricky C.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Hetherington; Ricky C..The latest application filed is for "extended main memory hierarchy having flash memory for page fault handling".

Company Profile

0.54.9

Hetherington; Ricky C. - Pleasanton CA
Hetherington; Ricky C. - Westboro MA
Hetherington; Ricky C. - Northboro MA
Hetherington; Ricky C. - Northborough MA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Extended main memory hierarchy having flash memory for page fault handling Grant 9,208,084 - Kapil , et al. December 8, 2	2015-12-08
Cache coherent support for flash in a memory hierarchy Grant 8,180,981 - Kapil , et al. May 15, 2	2012-05-15
Multiple-core processor with support for multiple virtual processors Grant 7,873,776 - Hetherington , et al. January 18, 2	2011-01-18
Extended Main Memory Hierarchy Having Flash Memory For Page Fault Handling App 20100332727 - Kapil; Sanjiv ; et al.	2010-12-30
Cache Coherent Support For Flash In A Memory Hierarchy App 20100293420 - Kapil; Sanjiv ; et al.	2010-11-18
Multiple-core, multithreaded processor with flexible error steering mechanism Grant 7,716,521 - Donahue , et al. May 11, 2	2010-05-11
Multiple-core processor with flexible mapping of processor cores to cache banks Grant 7,685,354 - Hetherington , et al. March 23, 2	2010-03-23
System interface unit Grant 7,644,221 - Chan , et al. January 5, 2	2010-01-05
ECC encoding for uncorrectable errors Grant 7,587,658 - Tong , et al. September 8, 2	2009-09-08
Use of FBDIMM channel as memory channel and coherence channel Grant 7,529,894 - Hetherington , et al. May 5, 2	2009-05-05
Processor and method for device-specific memory address translation Grant 7,487,327 - Chang , et al. February 3, 2	2009-02-03
Apparatus and method for fine-grained multithreading in a multipipelined processor core Grant 7,401,206 - Hetherington , et al. July 15, 2	2008-07-15
Multi-socket symmetric multiprocessing (SMP) system for chip multi-threaded (CMT) processors Grant 7,398,360 - Hetherington , et al. July 8, 2	2008-07-08
Precise error handling in a fine grain multithreaded multicore processor Grant 7,370,243 - Grohoski , et al. May 6, 2	2008-05-06
Multiple independent coherence planes for maintaining coherency Grant 7,353,340 - Hetherington , et al. April 1, 2	2008-04-01
Method and apparatus for power throttling in a multi-thread processor Grant 7,330,988 - Golla , et al. February 12, 2	2008-02-12
Multiple-core processor with flexible cache directory scheme Grant 7,240,160 - Hetherington , et al. July 3, 2	2007-07-03
Multiple independent coherence planes for maintaining coherency App 20070043911 - Hetherington; Ricky C. ; et al.	2007-02-22
Use of FBDIMM Channel as memory channel and coherence channel App 20070043913 - Hetherington; Ricky C. ; et al.	2007-02-22
Multi-socked symmetric multiprocessing (SMP) system for chip multi-threaded (CMT) processors App 20070043912 - Hetherington; Ricky C. ; et al.	2007-02-22
Method and appratus for power throttling in a multi-thread processor App 20060020831 - Golla; Robert T. ; et al.	2006-01-26
Apparatus and method for fine-grained multithreading in a multipipelined processor core App 20060004995 - Hetherington; Ricky C. ; et al.	2006-01-05
Multiple-core processor with support for multiple virtual processors App 20060004942 - Hetherington; Ricky C. ; et al.	2006-01-05
Method for operating a non-blocking hierarchical cache throttle Grant 6,684,299 - Hetherington , et al. January 27, 2	2004-01-27
Mechanism for reordering transactions in computer systems with snoop-based cache consistency protocols Grant 6,484,240 - Cypher , et al. November 19, 2	2002-11-19
Apparatus and method for distributed non-blocking multi-level cache Grant 6,430,654 - Mehrotra , et al. August 6, 2	2002-08-06
Apparatus for determining memory bank availability in a computer system Grant 6,360,285 - Fenwick , et al. March 19, 2	2002-03-19
Method for operating a non-blocking hierarchical cache throttle Grant 6,269,426 - Hetherington , et al. July 31, 2	2001-07-31
Method for operating a non-blocking hierarchical cache throttle App 20010010069 - Hetherington, Ricky C. ; et al.	2001-07-26
Apparatus for dynamically reconfiguring a processor Grant 6,240,502 - Panwar , et al. May 29, 2	2001-05-29
Method and apparatus for moderating current demand in an integrated circuit processor Grant 6,219,723 - Hetherington , et al. April 17, 2	2001-04-17
Cache tag caching Grant 6,212,602 - Wicki , et al. April 3, 2	2001-04-03
Non-blocking hierarchical cache throttle Grant 6,154,815 - Hetherington , et al. November 28, 2	2000-11-28
Method for inhibiting thrashing in a multi-level non-blocking cache system Grant 6,154,812 - Hetherington , et al. November 28, 2	2000-11-28
Apparatus and method for handling multiple mergeable misses in a non-blocking cache Grant 6,145,054 - Mehrotra , et al. November 7, 2	2000-11-07
Speculative cache line write backs to avoid hotspots Grant 6,119,205 - Wicki , et al. September 12, 2	2000-09-12
Distributed data bus sequencing for a system bus with separate address and data bus protocols Grant 6,076,129 - Fenwick , et al. June 13, 2	2000-06-13
Apparatus for maintaining program correctness while allowing loads to be boosted past stores in an out-of-order machine Grant 6,058,472 - Panwar , et al. May 2, 2	2000-05-02
Method for non-intrusive cache fills and handling of load misses Grant 6,052,775 - Panwar , et al. April 18, 2	2000-04-18
Apparatus for restraining over-eager load boosting in an out-of-order machine using a memory disambiguation buffer for determining dependencies Grant 6,006,326 - Panwar , et al. December 21, 1	1999-12-21
Method for restraining over-eager load boosting using a dependency color indicator stored in cache with both the load and store instructions Grant 5,999,727 - Panwar , et al. December 7, 1	1999-12-07
Inclusion vector architecture for a level two cache Grant 5,996,048 - Cherabuddi , et al. November 30, 1	1999-11-30
Apparatus for executing coded dependent instructions having variable latencies Grant 5,987,594 - Panwar , et al. November 16, 1	1999-11-16
Method for thermal overload detection and prevention for an intergrated circuit processor Grant 5,978,864 - Hetherington , et al. November 2, 1	1999-11-02
System for thermal overload detection and prevention for an integrated circuit processor Grant 5,948,106 - Hetherington , et al. September 7, 1	1999-09-07
Method for performing in-line bank conflict detection and resolution in a multi-ported non-blocking cache Grant 5,930,819 - Hetherington , et al. July 27, 1	1999-07-27
Reducing cache misses by snarfing writebacks in non-inclusive memory systems Grant 5,909,697 - Hayes , et al. June 1, 1	1999-06-01
Method for dynamically reconfiguring a processor Grant 5,890,008 - Panwar , et al. March 30, 1	1999-03-30
Distributed data bus sequencing for a system bus with separate address and data bus protocols Grant 5,666,551 - Fenwick , et al. September 9, 1	1997-09-09
Delay compensated signal propagation Grant 5,475,690 - Burns , et al. December 12, 1	1995-12-12
System for translation of virtual to physical addresses by operating memory management processor for calculating location of physical address in memory concurrently with cache comparing virtual addresses for translation Grant 5,349,651 - Hetherington , et al. September 20, 1	1994-09-20
Integrated circuit chip having primary and secondary random access memories for a hierarchical cache Grant 5,285,323 - Hetherington , et al. February 8, 1	1994-02-08
Scheme for insuring data consistency between a plurality of cache memories and the main memory in a multi-processor system Grant 5,222,224 - Flynn , et al. June 22, 1	1993-06-22
Method and apparatus for ordering and queueing multiple memory requests Grant 5,222,223 - Webb, Jr. , et al. June 22, 1	1993-06-22
System for queuing individual read or write mask and generating respective composite mask for controlling access to general purpose register Grant 5,142,631 - Murray , et al. August 25, 1	1992-08-25
Method and apparatus for resolving a variable number of potential memory access conflicts in a pipelined computer system Grant 5,125,083 - Fite , et al. June 23, 1	1992-06-23
Virtual instruction cache system using length responsive decoded instruction shifting and merging with prefetch buffer outputs to fill instruction buffer Grant 5,113,515 - Fite , et al. May 12, 1	1992-05-12
Method and apparatus for increasing the data storage rate of a computer system having a predefined data path width Grant 5,019,965 - Webb, Jr. , et al. May 28, 1	1991-05-28
Write back buffer with error correcting capabilities Grant 4,995,041 - Hetherington , et al. February 19, 1	1991-02-19
System for delaying processing of memory access exceptions until the execution stage of an instruction pipeline of a virtual memory system based digital computer Grant 4,985,825 - Webb, Jr. , et al. January 15, 1	1991-01-15
Method and apparatus for detecting and correcting errors in a pipelined computer system Grant 4,982,402 - Beaven , et al. January 1, 1	1991-01-01
Method and apparatus using a cache and main memory for both vector processing and scalar processing by prefetching cache blocks including vector data elements Grant 4,888,679 - Fossum , et al. December 19, 1	1989-12-19

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