| Patent | Date |
|---|
Pipelined computer system with power management control
Grant 7,900,075 - Maher , et al. March 1, 2 | 2011-03-01 |
Power management method for a pipelined computer system
Grant 7,900,076 - Maher , et al. March 1, 2 | 2011-03-01 |
Instruction-initiated method for suspending operation of a pipelined data processor
Grant 7,509,512 - Maher , et al. March 24, 2 | 2009-03-24 |
Power management method for a pipelined computer system
App 20080109667 - Maher; Robert ; et al. | 2008-05-08 |
Pipelined computer system with power management control
App 20080098248 - Maher; Robert ; et al. | 2008-04-24 |
Instruction-initiated power management method for a pipelined data processor
Grant 7,120,810 - Maher , et al. October 10, 2 | 2006-10-10 |
Signal-initiated method for suspending operation of a pipelined data processor
Grant 7,062,666 - Maher , et al. June 13, 2 | 2006-06-13 |
Signal-initiated power management method for a pipelined data processor
Grant 7,000,132 - Maher , et al. February 14, 2 | 2006-02-14 |
Pipelined data processor with instruction-initiated power management control
Grant 6,978,390 - Maher , et al. December 20, 2 | 2005-12-20 |
Pipelined data processor with signal-initiated power management control
Grant 6,910,141 - Maher , et al. June 21, 2 | 2005-06-21 |
Instruction-initiated method for suspending operation of a pipelined data pocessor
App 20050036261 - Maher, Robert ; et al. | 2005-02-17 |
Instruction-initiated power management method for a pipelined data processor
App 20050024802 - Maher, Robert ; et al. | 2005-02-03 |
Pipelined data processor with instruction-initiated power management control
App 20040230852 - Maher, Robert ; et al. | 2004-11-18 |
Pipelined data processor with signal-initiated power management control
App 20040172572 - Maher, Robert ; et al. | 2004-09-02 |
Signal-initiated method for suspending operation of a pipelined data processor
App 20040172568 - Maher, Robert ; et al. | 2004-09-02 |
Signal-initiated power management method for a pipelined data processor
App 20040172567 - Maher, Robert ; et al. | 2004-09-02 |
Method For Controlling Power Of A Microprocessor By Asserting And De-asserting A Control Signal In Response Conditions Associated With The Microprocessor Entering And Exiting Low Power State Respectively
Grant 6,721,894 - Maher , et al. April 13, 2 | 2004-04-13 |
System For Controlling Power Of A Microprocessor By Asserting And De-asserting A Control Signal In Response To Condition Associated With The Microprocessor Entering And Exiting Low Power State Respectively
Grant 6,694,443 - Maher , et al. February 17, 2 | 2004-02-17 |
Microprocessor power management control method
App 20030084355 - Maheb, Robert ; et al. | 2003-05-01 |
Method of invoking a low power mode in a computer system using a halt instruction
Grant 6,343,363 - Maher , et al. January 29, 2 | 2002-01-29 |
Computer system with low power mode invoked by halt instruction
Grant 6,088,807 - Maher , et al. July 11, 2 | 2000-07-11 |
Coherency for write-back cache in a system designed for write-through cache including export-on-hold
Grant 5,860,111 - Martinez, Jr. , et al. January 12, 1 | 1999-01-12 |
Coherency for write-back cache in a system designed for write-through cache using an export/invalidate protocol
Grant 5,664,149 - Martinez, Jr. , et al. September 2, 1 | 1997-09-02 |
Microprocessor having power management circuitry with coprocessor support
Grant 5,632,037 - Maher , et al. May 20, 1 | 1997-05-20 |
Microprocessor with externally controllable power management
Grant 5,630,143 - Maher , et al. May 13, 1 | 1997-05-13 |
Coherency for write-back cache in a system designed for write-through cache including write-back latency control
Grant 5,524,234 - Martinez, Jr. , et al. June 4, 1 | 1996-06-04 |
Microprocessor for selectively configuring pinout by activating tri-state device to disable internal clock from external pin
Grant 5,375,209 - Maher , et al. December 20, 1 | 1994-12-20 |
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