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Patent applications and USPTO patent grants for Her; Jaw-Kang.The latest application filed is for "shallow trench isolation structure with low sidewall capacitance for high speed integrated circuits".
Patent | Date |
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Method for extracting and modeling semiconductor device series resistance and for simulating a semiconductor device with use thereof Grant 7,421,383 - Hsiao , et al. September 2, 2 | 2008-09-02 |
Shallow trench isolation structure with low sidewall capacitance for high speed integrated circuits Grant 7,141,485 - Su , et al. November 28, 2 | 2006-11-28 |
Shallow trench isolation structure with low sidewall capacitance for high speed integrated circuits App 20040251513 - Su, Ke-Wei ;   et al. | 2004-12-16 |
Characterization methodology for the thin gate oxide device Grant 6,800,496 - Chiang , et al. October 5, 2 | 2004-10-05 |
Method for extracting and modeling semiconductor device series resistance and for simulating a semiconductor device with use thereof App 20040138865 - Hsiao, Cheng ;   et al. | 2004-07-15 |
SOI MOSFET with compact body-tied-source structure App 20030222308 - Su, Ke-Wei ;   et al. | 2003-12-04 |
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