loadpatents
name:-0.023649930953979
name:-0.016236066818237
name:-0.00051403045654297
Heo; Nak-Won Patent Filings

Heo; Nak-Won

Patent Applications and Registrations

Patent applications and USPTO patent grants for Heo; Nak-Won.The latest application filed is for "semiconductor memory devices including redundancy memory cells".

Company Profile
0.16.20
  • Heo; Nak-Won - Hwaseong-si KR
  • Heo; Nak-Won - Gyeonggi-do N/A KR
  • Heo; Nak-Won - Suwon-si KR
  • Heo; Nak-won - Suwon KR
  • Heo; Nak-Won - Kyungki-do KR
  • Heo; Nak-Won - Yongin-shi KR
  • Heo, Nak-won - Suwon-city KR
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Semiconductor memory devices including redundancy memory cells
Grant 9,858,981 - Lee , et al. January 2, 2
2018-01-02
Semiconductor Memory Devices Including Redundancy Memory Cells
App 20170092349 - Lee; Yun-Young ;   et al.
2017-03-30
Semiconductor Memory Devices Including Redundancy Memory Cells
App 20160247553 - LEE; Yun-Young ;   et al.
2016-08-25
Semiconductor memory devices including redundancy memory cells
Grant 9,336,906 - Lee , et al. May 10, 2
2016-05-10
Semiconductor Memory Devices Including Redundancy Memory Cells
App 20150221361 - Lee; Yun-Young ;   et al.
2015-08-06
Semiconductor Memory Device For Performing Disable Operation Using Anti-fuse And Method Thereof
App 20140241085 - RYU; Je-Min ;   et al.
2014-08-28
Otp Cell Array Including Protected Area, Semiconductor Memory Device Including The Same, And Method Of Programming The Same
App 20140219000 - OH; Chi-Sung ;   et al.
2014-08-07
Semiconductor memory devices and systems including data output circuits to output stored data during first output mode and output programmed data pattern during second output mode
Grant 8,625,364 - Heo January 7, 2
2014-01-07
Semiconductor Memory Device And Methods Thereof
App 20120230125 - HEO; Nak-Won
2012-09-13
Semiconductor memory device with a data output circuit configured to output stored data during a first type of read operation and configured to output at least one data pattern during a second type of read operation and methods thereof
Grant 8,199,588 - Heo June 12, 2
2012-06-12
Semiconductor memory device and methods thereof
App 20090244986 - Heo; Nak-Won
2009-10-01
Data output circuit and method in DDR synchronous semiconductor device
Grant 7,558,127 - Heo , et al. July 7, 2
2009-07-07
Semiconductor memory device with a data output circuit configured to output stored data during a first type of read operation and configured to output at least one data pattern during a second type of read operation and methods thereof
Grant 7,551,495 - Heo June 23, 2
2009-06-23
Semiconductor memory device with strengthened power and method of strengthening power of the same
Grant 7,518,898 - Bae , et al. April 14, 2
2009-04-14
Semiconductor memory device and method of supplying wordline voltage thereof
Grant 7,447,084 - Heo , et al. November 4, 2
2008-11-04
Data Output Circuit And Method In Ddr Synchronous Semiconductor Device
App 20080225606 - HEO; Nak-Won ;   et al.
2008-09-18
Semiconductor memory device with fail-bit storage unit and method for parallel bit testing
App 20080215939 - Ahn; Ji-Hyun ;   et al.
2008-09-04
Data output circuit and method in DDR synchronous semiconductor device
Grant 7,376,021 - Heo , et al. May 20, 2
2008-05-20
Semiconductor Memory Device With Data And Local Redundancy Memory Cell Arrays, And Redundancy Method Thereof
App 20080049526 - JUNG; Han-Gyun ;   et al.
2008-02-28
Semiconductor memory device and methods thereof
App 20070168631 - Heo; Nak-Won
2007-07-19
Semiconductor memory device with strengthened power and method of strengthening power of the same
App 20060181913 - Bae; Chang-Hyun ;   et al.
2006-08-17
Semiconductor memory device and method of supplying wordline voltage thereof
App 20060146616 - Heo; Nak-Won ;   et al.
2006-07-06
Delay locked loop capable of compensating for delay of internal clock signal by variation of driving strength of output driver in semiconductor memory device
Grant 7,068,084 - Byun , et al. June 27, 2
2006-06-27
Circuit for generating a data strobe signal used in a double data rate synchronous semiconductor device
Grant 6,940,321 - Heo , et al. September 6, 2
2005-09-06
Information processing system with memory modules of a serial bus architecture
Grant 6,839,786 - Kim , et al. January 4, 2
2005-01-04
Circuit for generating a data strobe signal used in a double data rate synchronous semiconductor device
App 20040145962 - Heo, Nak-Won ;   et al.
2004-07-29
Delay locked loop capable of compensating for delay of internal clock signal by variation of driving strength of output driver in semiconductor memory device
App 20040124896 - Byun, Gyung-su ;   et al.
2004-07-01
Data output circuit and method in DDR synchronous semiconductor device
App 20040098551 - Heo, Nak-Won ;   et al.
2004-05-20
Data output method and data output circuit for applying reduced precharge level
Grant 6,717,448 - Heo , et al. April 6, 2
2004-04-06
Delay locked loop circuit and method having adjustable locking resolution
Grant 6,621,315 - Heo , et al. September 16, 2
2003-09-16
Data output method and data output circuit for applying reduced precharge level
App 20030094985 - Heo, Nak-won ;   et al.
2003-05-22
Delay locked loop circuit and method having adjustable locking resolution
App 20030085744 - Heo, Nak Won ;   et al.
2003-05-08
Information processing system with memory modules of a serial bus architecture
App 20020194416 - Kim, Kyung-Ho ;   et al.
2002-12-19

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