| Patent | Date |
|---|
Neural network unit that interrupts processing core upon condition
Grant 11,226,840 - Henry , et al. January 18, 2 | 2022-01-18 |
Neural network unit that interrupts processing core upon condition
Grant 11,221,872 - Henry , et al. January 11, 2 | 2022-01-11 |
Neural network unit that manages power consumption based on memory accesses per period
Grant 11,216,720 - Henry January 4, 2 | 2022-01-04 |
Processor with memory controller including dynamically programmable functional unit
Grant 11,061,853 - Henry , et al. July 13, 2 | 2021-07-13 |
Neural network unit
Grant 11,029,949 - Henry , et al. June 8, 2 | 2021-06-08 |
Neural network unit with plurality of selectable output functions
Grant 10,776,690 - Henry , et al. Sept | 2020-09-15 |
Processor with selective data storage (of accelerator) operable as either victim cache data storage or accelerator memory and having victim cache tags in lower level cache wherein evicted cache line is stored in said data storage when said data storage is
Grant 10,725,934 - Henry , et al. | 2020-07-28 |
Neural network unit that performs convolutions using collective shift register among array of neural processing units
Grant 10,671,564 - Henry , et al. | 2020-06-02 |
Processor with memory array operable as either cache memory or neural network unit memory
Grant 10,664,751 - Henry , et al. | 2020-05-26 |
Processor with an expandable instruction set architecture for dynamically configuring execution resources
Grant 10,642,617 - Henry , et al. | 2020-05-05 |
Dynamic reconfiguration of multi-core processor
Grant 10,635,453 - Henry , et al. | 2020-04-28 |
Neural network unit with re-shapeable memory
Grant 10,586,148 - Henry , et al. | 2020-03-10 |
Processor with hybrid coprocessor/execution unit neural network unit
Grant 10,585,848 - Henry , et al. | 2020-03-10 |
Neural network unit with segmentable array width rotator
Grant 10,565,494 - Henry , et al. Feb | 2020-02-18 |
Neural network unit with segmentable array width rotator
Grant 10,565,492 - Henry , et al. Feb | 2020-02-18 |
Neural network unit with output buffer feedback for performing recurrent neural network computations
Grant 10,552,370 - Henry , et al. Fe | 2020-02-04 |
Neural network unit with mixed data and weight size computation capability
Grant 10,515,302 - Henry , et al. Dec | 2019-12-24 |
Neural processing unit that selectively writes back to neural memory either activation function output or accumulator value
Grant 10,509,765 - Henry , et al. Dec | 2019-12-17 |
Neural network unit with neural memory and array of neural processing units that collectively shift row of data received from neural memory
Grant 10,474,627 - Henry , et al. Nov | 2019-11-12 |
Processor with variable rate execution unit
Grant 10,474,628 - Henry , et al. Nov | 2019-11-12 |
Neural network unit with memory layout to perform efficient 3-dimensional convolutions
Grant 10,438,115 - Henry , et al. O | 2019-10-08 |
Processor with memory array operable as either last level cache slice or neural network unit memory
Grant 10,430,706 - Henry , et al. O | 2019-10-01 |
Asymmetric multi-core processor with native switching mechanism
Grant 10,423,216 - Hooker , et al. Sept | 2019-09-24 |
Processor with memory array operable as either victim cache or neural network unit memory
Grant 10,423,876 - Henry , et al. Sept | 2019-09-24 |
Neural network unit that performs efficient 3-dimensional convolutions
Grant 10,417,560 - Henry , et al. Sept | 2019-09-17 |
Neural network unit with neural memory and array of neural processing units and sequencer that collectively shift row of data received from neural memory
Grant 10,409,767 - Henry , et al. Sept | 2019-09-10 |
Domain-differentiated power state coordination system
Grant 10,409,347 - Henry , et al. Sept | 2019-09-10 |
Microprocessor that fuses if-then instructions
Grant 10,394,562 - Henry , et al. A | 2019-08-27 |
Neural network unit with neural memory and array of neural processing units that collectively perform multi-word distance rotates of row of data received from neural memory
Grant 10,395,165 - Henry , et al. A | 2019-08-27 |
Neural network unit with shared activation function units
Grant 10,387,366 - Henry , et al. A | 2019-08-20 |
Neural network unit employing user-supplied reciprocal for normalizing an accumulated value
Grant 10,380,064 - Henry , et al. A | 2019-08-13 |
Neural network unit that performs concurrent LSTM cell calculations
Grant 10,380,481 - Henry , et al. A | 2019-08-13 |
Multi-operation neural network unit
Grant 10,366,050 - Henry , et al. July 30, 2 | 2019-07-30 |
Mechanism for communication between architectural program running on processor and non-architectural program running on execution unit of the processor regarding shared resource
Grant 10,353,861 - Henry , et al. July 16, 2 | 2019-07-16 |
Neural network unit with neural processing units dynamically configurable to process multiple data sizes
Grant 10,353,860 - Henry , et al. July 16, 2 | 2019-07-16 |
Neural network unit that performs stochastic rounding
Grant 10,353,862 - Henry , et al. July 16, 2 | 2019-07-16 |
Direct execution by an execution unit of a micro-operation loaded into an architectural register file by an architectural instruction of a processor
Grant 10,346,350 - Henry , et al. July 9, 2 | 2019-07-09 |
Neural network unit with output buffer feedback and masking capability with processing unit groups that operate as recurrent neural network LSTM cells
Grant 10,346,351 - Henry , et al. July 9, 2 | 2019-07-09 |
Neural network unit with output buffer feedback and masking capability
Grant 10,282,348 - Henry , et al. | 2019-05-07 |
Processor with architectural neural network execution unit
Grant 10,275,394 - Henry , et al. | 2019-04-30 |
Tri-configuration neural network unit
Grant 10,275,393 - Henry , et al. | 2019-04-30 |
Processor with programmable prefetcher operable to generate at least one prefetch address based on load requests
Grant 10,268,586 - Henry , et al. | 2019-04-23 |
Processor with programmable prefetcher operable to generate at least one prefetch address based on load requests
Grant 10,268,587 - Henry , et al. | 2019-04-23 |
Domain-Differentiated Power State Coordination System
App 20190107873 - Henry; G. Glenn ; et al. | 2019-04-11 |
Dynamic Reconfiguration of Multi-core Processor
App 20190095216 - Henry; G. Glenn ; et al. | 2019-03-28 |
Processor with approximate computing execution unit that includes an approximation control register having an approximation mode flag, an approximation amount, and an error threshold, where the approximation control register is writable by an instruction set instruction
Grant 10,235,232 - Henry , et al. | 2019-03-19 |
Apparatus and method for programmable load replay preclusion
Grant 10,228,944 - Col , et al. | 2019-03-12 |
Apparatus employing user-specified binary point fixed point arithmetic
Grant 10,228,911 - Henry , et al. | 2019-03-12 |
Compressing instruction queue for a microprocessor
Grant 10,216,520 - Day , et al. Feb | 2019-02-26 |
Apparatus and method for programmable load replay preclusion
Grant 10,209,996 - Col , et al. Feb | 2019-02-19 |
Dynamic cache enlarging by counting evictions
Grant 10,204,056 - Henry , et al. Feb | 2019-02-12 |
Dynamic reconfiguration of multi-core processor
Grant 10,198,269 - Henry , et al. Fe | 2019-02-05 |
Apparatus and method to preclude non-core cache-dependent load replays in an out-of-order processor
Grant 10,175,984 - Col , et al. J | 2019-01-08 |
Domain-differentiated power state coordination system
Grant 10,175,732 - Henry , et al. J | 2019-01-08 |
Apparatus and method to preclude non-core cache-dependent load replays in an out-of-order processor
Grant 10,146,547 - Col , et al. De | 2018-12-04 |
Apparatus and method to preclude load replays dependent on write combining memory space access in an out-of-order processor
Grant 10,146,540 - Col , et al. De | 2018-12-04 |
Load replay precluding mechanism
Grant 10,146,539 - Col , et al. De | 2018-12-04 |
Conversion system for a processor with an expandable instruction set architecture for dynamically configuring execution resources
Grant 10,146,543 - Henry , et al. De | 2018-12-04 |
Load replay precluding mechanism
Grant 10,146,546 - Col , et al. De | 2018-12-04 |
Neural network unit with segmentable array width rotator and re-shapeable weight memory to match segment width to provide common weights to multiple rotator segments
Grant 10,140,574 - Henry , et al. Nov | 2018-11-27 |
Apparatus and method to preclude load replays dependent on write combining memory space access in an out-of-order processor
Grant 10,133,580 - Col , et al. November 20, 2 | 2018-11-20 |
Mechanism to preclude uncacheable-dependent load replays in out-of-order processor
Grant 10,133,579 - Col , et al. November 20, 2 | 2018-11-20 |
Mechanism to preclude uncacheable-dependent load replays in out-of-order processor
Grant 10,127,046 - Col , et al. November 13, 2 | 2018-11-13 |
Compiler system for a processor with an expandable instruction set architecture for dynamically configuring execution resources
Grant 10,127,041 - Henry , et al. November 13, 2 | 2018-11-13 |
Method of managing power consumption within a multi-core microprocessor utilizing an inter-core state discovery process to identify a least power-conserving target core state of all of the cores that share the resource
Grant 10,126,793 - Henry , et al. November 13, 2 | 2018-11-13 |
Mechanism to preclude load replays dependent on off-die control element access in an out-of-order processor
Grant 10,120,689 - Col , et al. November 6, 2 | 2018-11-06 |
Programmable load replay precluding mechanism
Grant 10,114,646 - Col , et al. October 30, 2 | 2018-10-30 |
Programmable load replay precluding mechanism
Grant 10,114,794 - Col , et al. October 30, 2 | 2018-10-30 |
Method and apparatus for waking a single core of a multi-core microprocessor, while maintaining most cores in a sleep state
Grant 10,108,431 - Henry , et al. October 23, 2 | 2018-10-23 |
Mechanism to preclude load replays dependent on long load cycles in an out-of-order processor
Grant 10,108,428 - Col , et al. October 23, 2 | 2018-10-23 |
Mechanism to preclude load replays dependent on long load cycles in an out-of-order processor
Grant 10,108,420 - Col , et al. October 23, 2 | 2018-10-23 |
Mechanism to preclude shared RAM-dependent load replays in an out-of-order processor
Grant 10,108,429 - Col , et al. October 23, 2 | 2018-10-23 |
Mechanism to preclude shared ram-dependent load replays in an out-of-order processor
Grant 10,108,421 - Col , et al. October 23, 2 | 2018-10-23 |
Mechanism to preclude load replays dependent on off-die control element access in an out-of-order processor
Grant 10,108,430 - Col , et al. October 23, 2 | 2018-10-23 |
Mechanism to preclude load replays dependent on fuse array access in an out-of-order processor
Grant 10,108,427 - Col , et al. October 23, 2 | 2018-10-23 |
Mechanism to preclude I/O-dependent load replays in an out-of-order processor
Grant 10,095,514 - Col , et al. October 9, 2 | 2018-10-09 |
Event-based apparatus and method for securing bios in a trusted computing system during execution
Grant 10,095,868 - Henry October 9, 2 | 2018-10-09 |
Event-based apparatus and method for securing BIOS in a trusted computing system during execution
Grant 10,089,470 - Henry October 2, 2 | 2018-10-02 |
Mechanism to preclude I/O-dependent load replays in an out-of-order processor
Grant 10,088,881 - Col , et al. October 2, 2 | 2018-10-02 |
Mechanism to preclude load replays dependent on fuse array access in an out-of-order processor
Grant 10,089,112 - Col , et al. October 2, 2 | 2018-10-02 |
Neural Network Unit That Interrupts Processing Core Upon Condition
App 20180276034 - HENRY; G. Glenn ; et al. | 2018-09-27 |
Neural Network Unit That Interrupts Processing Core Upon Condition
App 20180276035 - HENRY; G. Glenn ; et al. | 2018-09-27 |
Neural Network Unit That Manages Power Consumption Based On Memory Accesses Per Period
App 20180276534 - HENRY; G. Glenn | 2018-09-27 |
Mechanism to preclude load replays dependent on page walks in an out-of-order processor
Grant 10,083,038 - Col , et al. September 25, 2 | 2018-09-25 |
Processor With Selective Data Storage Operable As Either Victim Cache Data Storage Or Accelerator Memory And Having Victim Cache Tags In Lower Level Cache
App 20180267898 - HENRY; G. Glenn ; et al. | 2018-09-20 |
Event-based apparatus and method for securing BIOS in a trusted computing system during execution
Grant 10,055,588 - Henry August 21, 2 | 2018-08-21 |
Event-based apparatus and method for securing bios in a trusted computing system during execution
Grant 10,049,217 - Henry August 14, 2 | 2018-08-14 |
Neural Network Unit
App 20180225116 - HENRY; G. Glenn ; et al. | 2018-08-09 |
Hardware data compressor that maintains sorted symbol list concurrently with input block scanning
Grant 10,027,346 - Henry July 17, 2 | 2018-07-17 |
Fingerprint units comparing stored static fingerprints with dynamically generated fingerprints and reconfiguring processor settings upon a fingerprint match
Grant 10,019,260 - Henry , et al. July 10, 2 | 2018-07-10 |
Neural Network Unit With Segmentable Array Width Rotator And Re-shapeable Weight Memory To Match Segment Width To Provide Common Weights To Multiple Rotator Segments
App 20180189651 - HENRY; G. GLENN ; et al. | 2018-07-05 |
Neural Network Unit With Re-shapeable Memory
App 20180189639 - HENRY; G. GLENN ; et al. | 2018-07-05 |
Neural Network Unit With Segmentable Array Width Rotator
App 20180189633 - HENRY; G. GLENN ; et al. | 2018-07-05 |
Neural Network Unit With Segmentable Array Width Rotator
App 20180189640 - HENRY; G. GLENN ; et al. | 2018-07-05 |
Neural Network Unit With Mixed Data And Weight Size Computation Capability
App 20180165575 - HENRY; G. GLENN ; et al. | 2018-06-14 |
Processor With Memory Array Operable As Either Cache Memory Or Neural Network Unit Memory
App 20180157970 - HENRY; G. GLENN ; et al. | 2018-06-07 |
Neural Network Unit With Neural Memory And Array Of Neural Processing Units That Collectively Perform Multi-word Distance Rotates Of Row Of Data Received From Neural Memory
App 20180157961 - HENRY; G. GLENN ; et al. | 2018-06-07 |
Processor With Memory Array Operable As Either Last Level Cache Slice Or Neural Network Unit Memory
App 20180157967 - HENRY; G. GLENN ; et al. | 2018-06-07 |
Neural Network Unit With Memory Layout To Perform Efficient 3-dimensional Convolutions
App 20180157962 - HENRY; G. GLENN ; et al. | 2018-06-07 |
Neural Network Unit That Performs Efficient 3-dimensional Convolutions
App 20180157966 - HENRY; G. GLENN ; et al. | 2018-06-07 |
Processor With Memory Array Operable As Either Victim Cache Or Neural Network Unit Memory
App 20180157968 - HENRY; G. GLENN ; et al. | 2018-06-07 |
Selective designation of multiple cores as bootstrap processor in a multi-core microprocessor
Grant 9,971,605 - Henry , et al. May 15, 2 | 2018-05-15 |
Key expansion logic using decryption key primitives
Grant 9,967,092 - Henry , et al. May 8, 2 | 2018-05-08 |
Centralized synchronization mechanism for a multi-core processor
Grant 9,952,654 - Henry , et al. April 24, 2 | 2018-04-24 |
Power saving mechanism to reduce load replays in out-of-order processor
Grant 9,915,998 - Col , et al. March 13, 2 | 2018-03-13 |
Microprocessor with on-the-fly switching of decryption keys
Grant 9,911,008 - Henry , et al. March 6, 2 | 2018-03-06 |
Event-based apparatus and method for securing bios in a trusted computing system during execution
Grant 9,910,991 - Henry March 6, 2 | 2018-03-06 |
Microprocessor with arm and X86 instruction length decoders
Grant 9,898,291 - Henry , et al. February 20, 2 | 2018-02-20 |
Multi-core hardware semaphore in non-architectural address space
Grant 9,898,303 - Henry , et al. February 20, 2 | 2018-02-20 |
Inter-core communication via uncore RAM
Grant 9,891,927 - Henry , et al. February 13, 2 | 2018-02-13 |
Decryption of encrypted instructions using keys selected on basis of instruction fetch address
Grant 9,892,283 - Henry , et al. February 13, 2 | 2018-02-13 |
Propagation of updates to per-core-instantiated architecturally-visible storage resource
Grant 9,891,928 - Henry , et al. February 13, 2 | 2018-02-13 |
Microprocessor That Fuses If-then Instructions
App 20180032341 - HENRY; G. GLENN ; et al. | 2018-02-01 |
Event-based apparatus and method for securing BIOS in a trusted computing system during execution
Grant 9,836,610 - Henry December 5, 2 | 2017-12-05 |
Event-based apparatus and method for securing bios in a trusted computing system during execution
Grant 9,836,609 - Henry December 5, 2 | 2017-12-05 |
Microprocessor using compressed and uncompressed microcode storage
Grant 9,830,155 - Henry , et al. November 28, 2 | 2017-11-28 |
Power management synchronization messaging system
Grant 9,829,945 - Henry , et al. November 28, 2 | 2017-11-28 |
Core ID designation system for dynamically designated bootstrap processor
Grant 9,811,344 - Henry , et al. November 7, 2 | 2017-11-07 |
Apparatus and method to preclude X86 special bus cycle load replays in an out-of-order processor
Grant 9,804,845 - Col , et al. October 31, 2 | 2017-10-31 |
Event-based apparatus and method for securing bios in a trusted computing system during execution
Grant 9,805,198 - Henry October 31, 2 | 2017-10-31 |
Processor With Memory Controller Including Dynamically Programmable Functional Unit
App 20170308314 - HENRY; G. GLENN ; et al. | 2017-10-26 |
Microprocessor with secure execution mode and store key instructions
Grant 9,798,898 - Henry , et al. October 24, 2 | 2017-10-24 |
Fuse-enabled secure bios mechanism with override feature
Grant 9,798,880 - Henry October 24, 2 | 2017-10-24 |
Microprocessor that fuses if-then instructions
Grant 9,792,121 - Parks , et al. October 17, 2 | 2017-10-17 |
Propagation of microcode patches to multiple cores in multicore microprocessor
Grant 9,792,112 - Henry , et al. October 17, 2 | 2017-10-17 |
Programmable secure bios mechanism in a trusted computing system
Grant 9,779,242 - Henry October 3, 2 | 2017-10-03 |
Fuse-enabled secure BIOS mechanism in a trusted computing system
Grant 9,779,243 - Henry October 3, 2 | 2017-10-03 |
Hardware data compressor using dynamic hash algorithm based on input block type
Grant 9,768,803 - Henry , et al. September 19, 2 | 2017-09-19 |
JTAG-based secure BIOS mechanism in a trusted computing system
Grant 9,767,288 - Henry September 19, 2 | 2017-09-19 |
Extended fuse reprogrammability mechanism
Grant 9,740,622 - Henry , et al. August 22, 2 | 2017-08-22 |
Apparatus and method to preclude X86 special bus cycle load replays in an out-of-order processor
Grant 9,740,271 - Col , et al. August 22, 2 | 2017-08-22 |
Core-specific fuse mechanism for a multi-core die
Grant 9,727,477 - Henry , et al. August 8, 2 | 2017-08-08 |
Apparatus and method for configurable redundant fuse banks
Grant 9,727,478 - Henry , et al. August 8, 2 | 2017-08-08 |
Multi-core fuse decompression mechanism
Grant 9,715,457 - Henry , et al. July 25, 2 | 2017-07-25 |
Apparatus and method for storage and decompression of configuration data
Grant 9,715,456 - Henry , et al. July 25, 2 | 2017-07-25 |
Apparatus and method for extended cache correction
Grant 9,710,390 - Henry , et al. July 18, 2 | 2017-07-18 |
Power saving mechanism to reduce load replays in out-of-order processor
Grant 9,703,359 - Col , et al. July 11, 2 | 2017-07-11 |
Multi-core data array power gating restoral mechanism
Grant 9,690,511 - Henry , et al. June 27, 2 | 2017-06-27 |
Processor With An Expandable Instruction Set Architecture For Dynamically Configuring Execution Resources
App 20170161067 - HENRY; G. GLENN ; et al. | 2017-06-08 |
Processor With Programmable Prefetcher
App 20170161196 - HENRY; G. GLENN ; et al. | 2017-06-08 |
Compiler System For A Processor With An Expandable Instruction Set Architecture For Dynamically Configuring Execution Resources
App 20170161036 - HENRY; G. GLENN ; et al. | 2017-06-08 |
Processor With Programmable Prefetcher
App 20170161195 - HENRY; G. GLENN ; et al. | 2017-06-08 |
Conversion System For A Processor With An Expandable Instruction Set Architecture For Dynamically Configuring Execution Resources
App 20170161037 - HENRY; G. GLENN ; et al. | 2017-06-08 |
Apparatus and method for repairing cache arrays in a multi-core microprocessor
Grant 9,665,490 - Henry , et al. May 30, 2 | 2017-05-30 |
Mechanism to preclude load replays dependent on page walks in an out-of-order processor
Grant 9,645,827 - Col , et al. May 9, 2 | 2017-05-09 |
Conditional store instructions in an out-of-order execution microprocessor
Grant 9,645,822 - Henry , et al. May 9, 2 | 2017-05-09 |
Hardware data compressor with multiple string match search hash tables each based on different hash size
Grant 9,628,111 - Henry , et al. April 18, 2 | 2017-04-18 |
Neural Network Unit That Performs Concurrent Lstm Cell Calculations
App 20170103305 - HENRY; G. Glenn ; et al. | 2017-04-13 |
Neural Network Unit With Output Buffer Feedback And Masking Capability With Processing Unit Groups That Operate As Recurrent Neural Network Lstm Cells
App 20170103312 - HENRY; G. GLENN ; et al. | 2017-04-13 |
Processor With Variable Rate Execution Unit
App 20170103040 - HENRY; G. GLENN ; et al. | 2017-04-13 |
Tri-configuration Neural Network Unit
App 20170103300 - HENRY; G. GLENN ; et al. | 2017-04-13 |
Direct Execution By An Execution Unit Of A Micro-operation Loaded Into An Architectural Register File By An Architectural Instruction Of A Processor
App 20170102945 - HENRY; G. GLENN ; et al. | 2017-04-13 |
Neural Network Unit With Output Buffer Feedback And Masking Capability
App 20170102941 - HENRY; G. GLENN ; et al. | 2017-04-13 |
Apparatus Employing User-specified Binary Point Fixed Point Arithmetic
App 20170102921 - HENRY; G. GLENN ; et al. | 2017-04-13 |
Neural Network Unit With Output Buffer Feedback For Performing Recurrent Neural Network Computations
App 20170103303 - HENRY; G. GLENN ; et al. | 2017-04-13 |
Neural Network Unit With Neural Memory And Array Of Neural Processing Units That Collectively Shift Row Of Data Received From Neural Memory
App 20170102940 - HENRY; G. GLENN ; et al. | 2017-04-13 |
Multi-operation Neural Network Unit
App 20170103310 - HENRY; G. GLENN ; et al. | 2017-04-13 |
Neural Network Unit With Plurality Of Selectable Output Functions
App 20170103304 - HENRY; G. GLENN ; et al. | 2017-04-13 |
Neural Network Unit That Performs Convolutions Using Collective Shift Register Among Array Of Neural Processing Units
App 20170103311 - HENRY; G. GLENN ; et al. | 2017-04-13 |
Neural Network Unit With Neural Processing Units Dynamically Configurable To Process Multiple Data Sizes
App 20170103302 - HENRY; G. GLENN ; et al. | 2017-04-13 |
Neural Network Unit With Shared Activation Function Units
App 20170103320 - HENRY; G. GLENN ; et al. | 2017-04-13 |
Mechanism For Communication Between Architectural Program Running On Processor And Non-architectural Program Running On Execution Unit Of The Processor Regarding Shared Resource
App 20170103041 - HENRY; G. GLENN ; et al. | 2017-04-13 |
Neural Processing Unit That Selectively Writes Back To Neural Memory Either Activation Function Output Or Accumulator Value
App 20170103319 - HENRY; G. GLENN ; et al. | 2017-04-13 |
Neural Network Unit Employing User-supplied Reciprocal For Normalizing An Accumulated Value
App 20170103321 - HENRY; G. GLENN ; et al. | 2017-04-13 |
Processor With Architectural Neural Network Execution Unit
App 20170103301 - HENRY; G. GLENN ; et al. | 2017-04-13 |
Neural Network Unit With Neural Memory And Array Of Neural Processing Units And Sequencer That Collectively Shift Row Of Data Received From Neural Memory
App 20170103306 - HENRY; G. GLENN ; et al. | 2017-04-13 |
Processor With Hybrid Coprocessor/execution Unit Neural Network Unit
App 20170103307 - HENRY; G. GLENN ; et al. | 2017-04-13 |
Neural Network Unit That Performs Stochastic Rounding
App 20170102920 - HENRY; G. GLENN ; et al. | 2017-04-13 |
Event-based Apparatus And Method For Securing Bios In A Trusted Computing System During Execution
App 20170098076 - HENRY; G. GLENN | 2017-04-06 |
Event-based Apparatus And Method For Securing Bios In A Trusted Computing System During Execution
App 20170098081 - HENRY; G. Glenn | 2017-04-06 |
Event-based Apparatus And Method For Securing Bios In A Trusted Computing System During Execution
App 20170098077 - HENRY; G. GLENN | 2017-04-06 |
Event-based Apparatus And Method For Securing Bios In A Trusted Computing System During Execution
App 20170098079 - HENRY; G. GLENN | 2017-04-06 |
Event-based Apparatus And Method For Securing Bios In A Trusted Computing System During Execution
App 20170098083 - HENRY; G. GLENN | 2017-04-06 |
Event-based Apparatus And Method For Securing Bios In A Trusted Computing System During Execution
App 20170098082 - HENRY; G. GLENN | 2017-04-06 |
Event-based Apparatus And Method For Securing Bios In A Trusted Computing System During Execution
App 20170098080 - HENRY; G. GLENN | 2017-04-06 |
Event-based Apparatus And Method For Securing Bios In A Trusted Computing System During Execution
App 20170098078 - HENRY; G. GLENN | 2017-04-06 |
Multi-core apparatus and method for restoring data arrays following a power gating event
Grant 9,606,933 - Henry , et al. March 28, 2 | 2017-03-28 |
Multi-core microprocessor power gating cache restoral programming mechanism
Grant 9,594,690 - Henry , et al. March 14, 2 | 2017-03-14 |
Multi-core programming apparatus and method for restoring data arrays following a power gating event
Grant 9,594,691 - Henry , et al. March 14, 2 | 2017-03-14 |
Multi-core Microprocessor That Dynamically Designates One Of Its Processing Cores As The Bootstrap Processor
App 20170068546 - HENRY; G. GLENN ; et al. | 2017-03-09 |
Multi-core processor having control unit that generates interrupt requests to all cores in response to synchronization condition
Grant 9,588,572 - Henry , et al. March 7, 2 | 2017-03-07 |
Processor that recovers from excessive approximate computing error
Grant 9,588,845 - Henry , et al. March 7, 2 | 2017-03-07 |
Multi-core programming apparatus and method for restoring data arrays following a power gating event
Grant 9,582,428 - Henry , et al. February 28, 2 | 2017-02-28 |
Multi-core data array power gating cache restoral programming mechanism
Grant 9,582,429 - Henry , et al. February 28, 2 | 2017-02-28 |
Propagation of updates to per-core-instantiated architecturally-visible storage resource
Grant 9,575,541 - Henry , et al. February 21, 2 | 2017-02-21 |
Jtag-based Secure Bios Mechanism In A Trusted Computing System
App 20170046515 - HENRY; G. GLENN | 2017-02-16 |
Fuse-enabled Secure Bios Mechanism In A Trusted Computing System
App 20170046516 - HENRY; G. GLENN | 2017-02-16 |
Fuse-enabled Secure Bios Mechanism With Override Feature
App 20170046517 - HENRY; G. GLENN | 2017-02-16 |
Programmable Secure Bios Mechanism In A Trusted Computing System
App 20170046514 - HENRY; G. GLENN | 2017-02-16 |
Event-based apparatus and method for securing bios in a trusted computing system during execution
Grant 9,547,767 - Henry January 17, 2 | 2017-01-17 |
Single-core Wakeup Multi-core Synchronization Mechanism
App 20170003707 - HENRY; G. GLENN ; et al. | 2017-01-05 |
Apparatus and method for compression of configuration data
Grant 9,535,847 - Henry , et al. January 3, 2 | 2017-01-03 |
Multi-core microprocessor that dynamically designates one of its processing cores as the bootstrap processor
Grant 9,535,488 - Henry , et al. January 3, 2 | 2017-01-03 |
Hardware Data Compressor Using Dynamic Hash Algorithm Based On Input Block Type
App 20160380649 - HENRY; G. GLENN ; et al. | 2016-12-29 |
Multi-core microprocessor power gating cache restoral mechanism
Grant 9,524,241 - Henry , et al. December 20, 2 | 2016-12-20 |
Mechanism To Preclude Load Replays Dependent On Fuse Array Access In An Out-of-order Processor
App 20160357568 - COL; GERARD M. ; et al. | 2016-12-08 |
Core synchronization mechanism in a multi-die multi-core microprocessor
Grant 9,513,687 - Henry , et al. December 6, 2 | 2016-12-06 |
Hardware data compressor that directly huffman encodes output tokens from LZ77 engine
Grant 9,515,678 - Henry , et al. December 6, 2 | 2016-12-06 |
Propagation Of Updates To Per-core-instantiated Architecturally-visible Storage Resource
App 20160349824 - HENRY; G. GLENN ; et al. | 2016-12-01 |
Apparatus And Method To Preclude X86 Special Bus Cycle Load Replays In An Out-of-order Processor
App 20160349825 - COL; Gerard M. ; et al. | 2016-12-01 |
Multi-core Data Array Power Gating Restoral Mechanism
App 20160350022 - HENRY; G. GLENN ; et al. | 2016-12-01 |
Mechanism To Preclude Load Replays Dependent On Long Load Cycles In An Out-of-order Processor
App 20160350120 - COL; GERARD M. ; et al. | 2016-12-01 |
Mechanism To Preclude Uncacheable-dependent Load Replays In Out-of-order Processor
App 20160350118 - COL; GERARD M. ; et al. | 2016-12-01 |
Mechanism To Preclude Load Replays Dependent On Off-die Control Element Access In An Out-of-order Processor
App 20160350127 - COL; Gerard M. ; et al. | 2016-12-01 |
Apparatus And Method To Preclude Non-core Cache-dependent Load Replays In An Out-of-order Processor
App 20160350121 - COL; GERARD M. ; et al. | 2016-12-01 |
Apparatus And Method For Programmable Load Replay Preclusion
App 20160350123 - COL; GERARD M. ; et al. | 2016-12-01 |
Load Replay Precluding Mechanism
App 20160350119 - COL; GERARD M. ; et al. | 2016-12-01 |
Apparatus And Method To Preclude Load Replays Dependent On Write Combining Memory Space Access In An Out-of-order Processor
App 20160350122 - COL; GERARD M. ; et al. | 2016-12-01 |
Mechanism To Preclude Load Replays Dependent On Page Walks In An Out-of-order Processor
App 20160350126 - COL; GERARD M. ; et al. | 2016-12-01 |
Hardware data compressor using dynamic hash algorithm based on input block type
Grant 9,509,337 - Henry , et al. November 29, 2 | 2016-11-29 |
Hardware data compressor that constructs and uses dynamic-prime huffman code tables
Grant 9,509,335 - Henry November 29, 2 | 2016-11-29 |
Hardware data compressor that pre-huffman encodes to decide whether to huffman encode a matched string or a back pointer thereto
Grant 9,509,336 - Henry November 29, 2 | 2016-11-29 |
Single core wakeup multi-core synchronization mechanism
Grant 9,507,404 - Henry , et al. November 29, 2 | 2016-11-29 |
Secure BIOS mechanism in a trusted computing system
Grant 9,507,942 - Henry November 29, 2 | 2016-11-29 |
Mechanism To Preclude I/o-dependent Load Replays In An Out-of-order Processor
App 20160342414 - COL; GERARD M. ; et al. | 2016-11-24 |
Mechanism To Preclude Shared Ram-dependent Load Replays In An Out-of-order Processor
App 20160342420 - COL; GERARD M. ; et al. | 2016-11-24 |
Hardware data compressor that sorts hash chains based on node string match probabilities
Grant 9,503,122 - Henry , et al. November 22, 2 | 2016-11-22 |
Hardware Data Compressor Using Dynamic Hash Algorithm Based On Input Block Type
App 20160336962 - HENRY; G. GLENN ; et al. | 2016-11-17 |
Hardware Data Compressor With Multiple String Match Search Hash Tables Each Based On Different Hash Size
App 20160336961 - HENRY; G. GLENN ; et al. | 2016-11-17 |
Hardware Data Compressor That Directly Huffman Encodes Output Tokens From Lz77 Engine
App 20160336960 - HENRY; G. GLENN ; et al. | 2016-11-17 |
Hardware Data Compressor That Maintains Sorted Symbol List Concurrently With Input Block Scanning
App 20160336958 - HENRY; G. GLENN | 2016-11-17 |
Hardware Data Compressor That Constructs And Uses Dynamic-prime Huffman Code Tables
App 20160336959 - HENRY; G. GLENN | 2016-11-17 |
Core-specific Fuse Mechanism For A Multi-core Die
App 20160321004 - HENRY; G. GLENN ; et al. | 2016-11-03 |
Apparatus And Method For Configurable Redundant Fuse Banks
App 20160321005 - HENRY; G. GLENN ; et al. | 2016-11-03 |
Apparatus And Method For Extended Cache Correction
App 20160321192 - HENRY; G. GLENN ; et al. | 2016-11-03 |
Uncore microcode ROM
Grant 9,483,263 - Henry , et al. November 1, 2 | 2016-11-01 |
Apparatus And Method For Storage And Decompression Of Configuration Data
App 20160314080 - HENRY; G. GLENN ; et al. | 2016-10-27 |
Multi-core Fuse Decompression Mechanism
App 20160313774 - HENRY; G. GLENN ; et al. | 2016-10-27 |
Apparatus and method for rapid fuse bank access in a multi-core processor
Grant 9,477,608 - Henry , et al. October 25, 2 | 2016-10-25 |
Extended Fuse Reprogrammability Mechanism
App 20160306695 - HENRY; G. GLENN ; et al. | 2016-10-20 |
Multi-core microprocessor configuration data compression and decompression system
Grant 9,471,502 - Henry , et al. October 18, 2 | 2016-10-18 |
Service processor patch mechanism
Grant 9,471,133 - Henry , et al. October 18, 2 | 2016-10-18 |
Multi-core synchronization mechanism
Grant 9,465,432 - Henry , et al. October 11, 2 | 2016-10-11 |
Method for encrypting a program for subsequent execution by a microprocessor configured to decrypt and execute the encrypted program
Grant 9,461,818 - Henry , et al. October 4, 2 | 2016-10-04 |
Running state power saving via reduced instructions per clock operation
Grant 9,442,732 - Henry , et al. September 13, 2 | 2016-09-13 |
Microprocessor Using Compressed And Uncompressed Microcode Storage
App 20160239303 - HENRY; G. GLENN ; et al. | 2016-08-18 |
Domain-differentiated Power State Coordination System
App 20160209913 - Henry; G. Glenn ; et al. | 2016-07-21 |
Power Saving Mechanism To Reduce Load Replays In Out-of-order Processor
App 20160209910 - COL; GERARD M. ; et al. | 2016-07-21 |
Power Management Synchronization Messaging System
App 20160209897 - HENRY; G. GLENN ; et al. | 2016-07-21 |
Core-specific fuse mechanism for a multi-core die
Grant 9,396,123 - Henry , et al. July 19, 2 | 2016-07-19 |
Apparatus and method for configurable redundant fuse banks
Grant 9,396,124 - Henry , et al. July 19, 2 | 2016-07-19 |
Multi-core data array power gating restoral mechanism
Grant 9,395,802 - Henry , et al. July 19, 2 | 2016-07-19 |
Microprocessor With Arm And X86 Instruction Length Decoders
App 20160202980 - HENRY; G. GLENN ; et al. | 2016-07-14 |
Apparatus and method for extended cache correction
Grant 9,390,022 - Henry , et al. July 12, 2 | 2016-07-12 |
Processor that performs approximate computing instructions
Grant 9,389,863 - Henry , et al. July 12, 2 | 2016-07-12 |
Apparatus and method for storage and decompression of configuration data
Grant 9,384,140 - Henry , et al. July 5, 2 | 2016-07-05 |
Multi-core fuse decompression mechanism
Grant 9,384,141 - Henry , et al. July 5, 2 | 2016-07-05 |
Conditional load instructions in an out-of-order execution microprocessor
Grant 9,378,019 - Henry , et al. June 28, 2 | 2016-06-28 |
Extended fuse reprogrammability mechanism
Grant 9,378,147 - Henry , et al. June 28, 2 | 2016-06-28 |
Multi-core Programming Apparatus And Method For Restoring Data Arrays Following A Power Gating Event
App 20160179689 - HENRY; G. GLENN ; et al. | 2016-06-23 |
Multi-core Programming Apparatus And Method For Restoring Data Arrays Following A Power Gating Event
App 20160179692 - HENRY; G. GLENN ; et al. | 2016-06-23 |
Power State Transitioning Procedure For A Multi-core Processor
App 20160179177 - HENRY; G. GLENN ; et al. | 2016-06-23 |
Multi-core Microprocessor Power Gating Cache Restoral Programming Mechanism
App 20160179691 - HENRY; G. GLENN ; et al. | 2016-06-23 |
Multi-core Data Array Power Gating Cache Restoral Programming Mechanism
App 20160179690 - HENRY; G. GLENN ; et al. | 2016-06-23 |
Microprocessor with compressed and uncompressed microcode memories
Grant 9,372,696 - Henry , et al. June 21, 2 | 2016-06-21 |
Mechanism To Preclude Load Replays Dependent On Off-die Control Element Access In An Out-of-order Processor
App 20160170761 - COL; GERARD M. ; et al. | 2016-06-16 |
Load Replay Precluding Mechanism
App 20160170754 - COL; GERARD M. ; et al. | 2016-06-16 |
Mechanism To Preclude Load Replays Dependent On Long Load Cycles In An Out-of-order Processor
App 20160170756 - COL; GERARD M. ; et al. | 2016-06-16 |
Programmable Load Replay Precluding Mechanism
App 20160170766 - COL; GERARD M. ; et al. | 2016-06-16 |
Apparatus And Method To Preclude Non-core Cache-dependent Load Replays In An Out-of-order Processor
App 20160170760 - COL; GERARD M. ; et al. | 2016-06-16 |
Mechanism To Preclude Load Replays Dependent On Page Walks In An Out-of-order Processor
App 20160170755 - COL; GERARD M. ; et al. | 2016-06-16 |
Apparatus And Method To Preclude X86 Special Bus Cycle Load Replays In An Out-of-order Processor
App 20160170762 - COL; GERARD M. ; et al. | 2016-06-16 |
Mechanism To Preclude I/o-dependent Load Replays In An Out-of-order Processor
App 20160170752 - COL; GERARD M. ; et al. | 2016-06-16 |
Mechanism To Preclude Uncacheable-dependent Load Replays In Out-of-order Processor
App 20160170753 - COL; GERARD M. ; et al. | 2016-06-16 |
Apparatus And Method To Preclude Load Replays Dependent On Write Combining Memory Space Access In An Out-of-order Processor
App 20160170763 - COL; GERARD M. ; et al. | 2016-06-16 |
Power Saving Mechanism To Reduce Load Replays In Out-of-order Processor
App 20160170758 - COL; GERARD M. ; et al. | 2016-06-16 |
Mechanism To Preclude Load Replays Dependent On Fuse Array Access In An Out-of-order Processor
App 20160170751 - COL; GERARD M. ; et al. | 2016-06-16 |
Mechanism To Preclude Shared Ram-dependent Load Replays In An Out-of-order Processor
App 20160170759 - COL; GERARD M. ; et al. | 2016-06-16 |
Apparatus And Method For Programmable Load Replay Preclusion
App 20160170764 - COL; GERARD M. ; et al. | 2016-06-16 |
Programmable Load Replay Precluding Mechanism
App 20160170757 - COL; GERARD M. ; et al. | 2016-06-16 |
Reconfigurably designating master core for conditional output on sideband communication wires distinct from system bus
Grant 9,367,497 - Henry , et al. June 14, 2 | 2016-06-14 |
Apparatus and method for securing BIOS in a trusted computing system
Grant 9,367,689 - Henry June 14, 2 | 2016-06-14 |
Centralized Synchronization Mechanism For A Multi-core Processor
App 20160162017 - HENRY; G. GLENN ; et al. | 2016-06-09 |
Asymmetric Processor With Cores That Support Different Isa Instruction Subsets
App 20160162293 - HOOKER; RODNEY E. ; et al. | 2016-06-09 |
Selectively compressed microcode
Grant 9,361,097 - Henry , et al. June 7, 2 | 2016-06-07 |
Correctable configuration data compression and decompression system
Grant 9,348,690 - Henry , et al. May 24, 2 | 2016-05-24 |
Microprocessor with boot indicator that indicates a boot ISA of the microprocessor as either the X86 ISA or the ARM ISA
Grant 9,317,301 - Henry , et al. April 19, 2 | 2016-04-19 |
Multi-core microprocessor that performs x86 ISA and ARM ISA machine language program instructions by hardware translation into microinstructions executed by common execution pipeline
Grant 9,317,288 - Henry , et al. April 19, 2 | 2016-04-19 |
Key Expansion Logic Using Decryption Key Primitives
App 20160105282 - HENRY; G. GLENN ; et al. | 2016-04-14 |
Microprocessor With On-the-fly Switching Of Decryption Keys
App 20160104011 - HENRY; G. GLENN ; et al. | 2016-04-14 |
Microprocessor With Secure Execution Mode And Store Key Instructions
App 20160104010 - HENRY; G. GLENN ; et al. | 2016-04-14 |
Decryption Of Encrypted Instructions Using Keys Selected On Basis Of Instruction Fetch Address
App 20160104009 - HENRY; G. GLENN ; et al. | 2016-04-14 |
Compressing Instruction Queue For A Microprocessor
App 20160098277 - DAY; MATTHEW DANIEL ; et al. | 2016-04-07 |
Distributed management of a shared clock source to a multi-core microprocessor
Grant 9,298,212 - Gaskins , et al. March 29, 2 | 2016-03-29 |
Conditional non-branch instruction prediction
Grant 9,274,795 - Henry , et al. March 1, 2 | 2016-03-01 |
Microprocessor that translates conditional load/store instructions into variable number of microinstructions
Grant 9,244,686 - Henry , et al. January 26, 2 | 2016-01-26 |
Microprocessor mechanism for decompression of cache correction data
Grant 9,223,715 - Henry , et al. December 29, 2 | 2015-12-29 |
Apparatus And Method For Repairing Cache Arrays In A Multi-core Microprocessor
App 20150339232 - HENRY; G. GLENN ; et al. | 2015-11-26 |
Multi-core Data Array Power Gating Restoral Mechanism
App 20150338905 - HENRY; G. GLENN ; et al. | 2015-11-26 |
Multi-core Apparatus And Method For Restoring Data Arrays Following A Power Gating Event
App 20150338904 - HENRY; G. GLENN ; et al. | 2015-11-26 |
Multi-core Microprocessor Power Gating Cache Restoral Mechanism
App 20150339231 - HENRY; G. GLENN ; et al. | 2015-11-26 |
Secure BIOS tamper protection mechanism
Grant 9,183,394 - Henry November 10, 2 | 2015-11-10 |
Load multiple and store multiple instructions in a microprocessor that emulates banked registers
Grant 9,176,733 - Henry , et al. November 3, 2 | 2015-11-03 |
Heterogeneous ISA microprocessor that preserves non-ISA-specific configuration state when reset to different ISA
Grant 9,146,742 - Henry , et al. September 29, 2 | 2015-09-29 |
Generating constant for microinstructions from modified immediate field during instruction translation
Grant 9,128,701 - Henry , et al. September 8, 2 | 2015-09-08 |
Partition-based apparatus and method for securing bios in a trusted computing system during execution
Grant 9,129,113 - Henry September 8, 2 | 2015-09-08 |
Processor With Approximate Computing Functional Unit
App 20150227407 - HENRY; G. GLENN ; et al. | 2015-08-13 |
Processor That Recovers From Excessive Approximate Computing Error
App 20150227429 - HENRY; G. GLENN ; et al. | 2015-08-13 |
Processor That Performs Approximate Computing Instructions
App 20150227372 - HENRY; G. GLENN ; et al. | 2015-08-13 |
Dynamic Cache Enlarging By Counting Evictions
App 20150212947 - Henry; G. Glenn ; et al. | 2015-07-30 |
Multi-core Microprocessor Configuration Data Compression And Decompression System
App 20150178218 - HENRY; G. GLENN ; et al. | 2015-06-25 |
Extended Fuse Reprogrammability Mechanism
App 20150179276 - HENRY; G. GLENN ; et al. | 2015-06-25 |
Multi-core Fuse Decompression Mechanism
App 20150178093 - HENRY; G. GLENN ; et al. | 2015-06-25 |
Core-specific Fuse Mechanism For A Multi-core Die
App 20150178216 - HENRY; G. GLENN ; et al. | 2015-06-25 |
Apparatus And Method For Extended Cache Correction
App 20150178215 - HENRY; G. GLENN ; et al. | 2015-06-25 |
Apparatus And Method For Storage And Decompression Of Configuration Data
App 20150178103 - HENRY; G. GLENN ; et al. | 2015-06-25 |
Apparatus And Method For Configurable Redundant Fuse Banks
App 20150178196 - HENRY; G. GLENN ; et al. | 2015-06-25 |
Apparatus And Method For Compression Of Configuration Data
App 20150169246 - HENRY; G. GLENN ; et al. | 2015-06-18 |
Apparatus And Method For Rapid Fuse Bank Access In A Multi-core Processor
App 20150170758 - HENRY; G. GLENN ; et al. | 2015-06-18 |
Accessing model specific registers (MSR) with different sets of distinct microinstructions for instructions of different instruction set architecture (ISA)
Grant 9,043,580 - Henry , et al. May 26, 2 | 2015-05-26 |
Event-based Apparatus And Method For Securing Bios In A Trusted Computing System During Execution
App 20150134976 - Henry; G. Glenn | 2015-05-14 |
Secure Bios Tamper Protection Mechanism
App 20150134978 - Henry; G. Glenn | 2015-05-14 |
Partition-based Apparatus And Method For Securing Bios In A Trusted Computing System During Execution
App 20150134977 - Henry; G. Glenn | 2015-05-14 |
Apparatus And Method For Securing Bios In A Trusted Computing System
App 20150134974 - Henry; G. Glenn | 2015-05-14 |
Secure Bios Mechanism In A Trusted Computing System
App 20150134975 - Henry; G. Glenn | 2015-05-14 |
Efficient conditional ALU instruction in read-port limited register file microprocessor
Grant 9,032,189 - Henry , et al. May 12, 2 | 2015-05-12 |
Selectively Compressed Microcode
App 20150113253 - Henry; G. Glenn ; et al. | 2015-04-23 |
Microprocessor With Compressed And Uncompressed Microcode Memories
App 20150113250 - Henry; G. Glenn ; et al. | 2015-04-23 |
Power state synchronization in a multi-core processor
Grant 9,009,512 - Henry , et al. April 14, 2 | 2015-04-14 |
On-die cryptographic apparatus in a secure microprocessor
Grant 9,002,014 - Henry , et al. April 7, 2 | 2015-04-07 |
Dynamically Reconfigurable Microprocessor
App 20150089204 - Henry; G. Glenn ; et al. | 2015-03-26 |
Apparatus and method for compression and decompression of microprocessor configuration data
Grant 8,982,655 - Henry , et al. March 17, 2 | 2015-03-17 |
Apparatus and method for managing a microprocessor providing for a secure execution mode
Grant 8,978,132 - Henry , et al. March 10, 2 | 2015-03-10 |
Single-core Wakeup Multi-core Synchronization Mechanism
App 20150067214 - Henry; G. Glenn ; et al. | 2015-03-05 |
Core Synchronization Mechanism In A Multi-die Multi-core Microprocessor
App 20150067368 - Henry; G. Glenn ; et al. | 2015-03-05 |
Microprocessor With Boot Indicator That Indicates A Boot Isa Of The Microprocessor As Either The X86 Isa Or The Arm Isa
App 20150067301 - HENRY; G. GLENN ; et al. | 2015-03-05 |
Propagation Of Updates To Per-core-instantiated Architecturally-visible Storage Resource
App 20150067307 - Henry; G. Glenn ; et al. | 2015-03-05 |
Service Processor Patch Mechanism
App 20150067263 - Henry; G. Glenn ; et al. | 2015-03-05 |
Multi-core Hardware Semaphore
App 20150067250 - Henry; G. Glenn ; et al. | 2015-03-05 |
Dynamic Designation Of The Bootstrap Processor In A Multi-core Microprocessor
App 20150067219 - Henry; G. Glenn ; et al. | 2015-03-05 |
Propagation Of Microcode Patches To Multiple Cores In Multicore Microprocessor
App 20150067666 - Henry; G. Glenn ; et al. | 2015-03-05 |
Selective Designation Of Multiple Cores As Bootstrap Processor In A Multi-core Microprocessor
App 20150067318 - Henry; G. Glenn ; et al. | 2015-03-05 |
Multi-core Synchronization Mechanism
App 20150067369 - Henry; G. Glenn ; et al. | 2015-03-05 |
Inter-core Communication Via Uncore Ram
App 20150067306 - Henry; G. Glenn ; et al. | 2015-03-05 |
Dynamic Reconfiguration Of Multi-core Processor
App 20150067310 - Henry; G. Glenn ; et al. | 2015-03-05 |
Multi-core Synchronization Mechanism With Interrupts On Sync Condition
App 20150067215 - Henry; G. Glenn ; et al. | 2015-03-05 |
Multi-core processor with core selectively disabled by kill instruction of system software and resettable only via external pin
Grant 8,972,707 - Henry , et al. March 3, 2 | 2015-03-03 |
Microprocessor Mechanism For Decompression Of Cache Correction Data
App 20150055428 - Henry; G. Glenn ; et al. | 2015-02-26 |
Correctable Configuration Data Compression And Decompression System
App 20150058695 - Henry; G. Glenn ; et al. | 2015-02-26 |
Multi-core Microprocessor Configuration Data Compression And Decompression System
App 20150055427 - Henry; G. Glenn ; et al. | 2015-02-26 |
Apparatus And Method For Extended Cache Correction
App 20150058564 - Henry; G. Glenn ; et al. | 2015-02-26 |
Extended Fuse Reprogrammability Mechanism
App 20150055395 - Henry; G. Glenn ; et al. | 2015-02-26 |
Apparatus And Method For Rapid Fuse Bank Access In A Multi-core Processor
App 20150054543 - Henry; G. Glenn ; et al. | 2015-02-26 |
Apparatus And Method For Storage And Decompression Of Configuration Data
App 20150058609 - Henry; G. Glenn ; et al. | 2015-02-26 |
Apparatus And Method For Compression And Decompression Of Microprocessor Configuration Data
App 20150055429 - Henry; G. Glenn ; et al. | 2015-02-26 |
Multi-core Fuse Decompression Mechanism
App 20150058563 - Henry; G. Glenn ; et al. | 2015-02-26 |
Core-specific Fuse Mechanism For A Multi-core Die
App 20150058610 - Henry; G. Glenn ; et al. | 2015-02-26 |
Apparatus And Method For Compression Of Configuration Data
App 20150058565 - Henry; G. Glenn ; et al. | 2015-02-26 |
Apparatus And Method For Configurable Redundant Fuse Banks
App 20150058598 - Henry; G. Glenn ; et al. | 2015-02-26 |
Dynamic And Selective Core Disablement And Reconfiguration In A Multi-core Processor
App 20150046680 - HENRY; G. GLENN ; et al. | 2015-02-12 |
Microprocessor with multicore processor power credit management feature
Grant 8,935,549 - Henry , et al. January 13, 2 | 2015-01-13 |
Master core discovering enabled cores in microprocessor comprising plural multi-core dies
Grant 8,930,676 - Henry , et al. January 6, 2 | 2015-01-06 |
Conditional ALU instruction condition satisfaction propagation between microinstructions in read-port limited register file microprocessor
Grant 8,924,695 - Henry , et al. December 30, 2 | 2014-12-30 |
Conditional ALU instruction condition satisfaction propagation between microinstructions in read-port limited register file microprocessor
Grant 08924695 - | 2014-12-30 |
Microprocessor That Fuses If-then Instructions
App 20140351561 - Parks; Terry ; et al. | 2014-11-27 |
Uncore Microcode Rom
App 20140297993 - Henry; G. Glenn ; et al. | 2014-10-02 |
Asymmetric Multi-core Processor With Native Switching Mechanism
App 20140298060 - Hooker; Rodney E. ; et al. | 2014-10-02 |
Microprocessor That Securely Decrypts And Executes Encrypted Instructions
App 20140195822 - Henry; G. Glenn ; et al. | 2014-07-10 |
Method For Encrypting A Program For Subsequent Execution By A Microprocessor Configured To Decrypt And Execute The Encrypted Program
App 20140195821 - Henry; G. Glenn ; et al. | 2014-07-10 |
Apparatus For Generating A Decryption Key For Use To Decrypt A Block Of Encrypted Instruction Data Being Fetched From An Instruction Cache In A Microprocessor
App 20140195820 - Henry; G. Glenn ; et al. | 2014-07-10 |
Microprocessor That Facilitates Task Switching Between Encrypted And Unencrypted Programs
App 20140195823 - Henry; G. Glenn ; et al. | 2014-07-10 |
Power State Synchronization In A Multi-core Processor
App 20140173301 - Henry; G. Glenn ; et al. | 2014-06-19 |
Distributed Management Of A Shared Clock Source To A Multi-core Microprocessor
App 20140164816 - Gaskins; Darius D. ; et al. | 2014-06-12 |
Microprocessor That Translates Conditional Load/store Instructions Into Variable Number Of Microinstructions
App 20140122847 - Henry; G. Glenn ; et al. | 2014-05-01 |
Conditional Store Instructions In An Out-of-order Execution Microprocessor
App 20140122843 - Henry; G. Glenn ; et al. | 2014-05-01 |
Revokeable Msr Password Protection
App 20140059358 - Henry; G. Glenn ; et al. | 2014-02-27 |
Conditional Load Instructions In An Out-of-order Execution Microprocessor
App 20140013089 - Henry; G. Glenn ; et al. | 2014-01-09 |
Running State Power Saving Via Reduced Instructions Per Clock Operation
App 20130311755 - Henry; G. Glenn ; et al. | 2013-11-21 |
Control Register Mapping In Heterogeneous Instruction Set Architecture Processor
App 20130067199 - Henry; G. Glenn ; et al. | 2013-03-14 |
Conditional Non-branch Instruction Prediction
App 20130067202 - Henry; G. Glenn ; et al. | 2013-03-14 |
Conditional Alu Instruction Pre-shift-generated Carry Flag Propagation Between Microinstructions In Read-port Limited Register File Microprocessor
App 20120260075 - Henry; G. Glenn ; et al. | 2012-10-11 |
Microprocessor That Performs X86 Isa And Arm Isa Machine Language Program Instructions By Hardware Translation Into Microinstructions Executed By Common Execution Pipeline
App 20120260067 - Henry; G. Glenn ; et al. | 2012-10-11 |
Conditional Alu Instruction Condition Satisfaction Propagation Between Microinstructions In Read-port Limited Register File Microprocessor
App 20120260071 - Henry; G. Glenn ; et al. | 2012-10-11 |
Heterogeneous Isa Microprocessor With Shared Hardware Isa Registers
App 20120260064 - Henry; G. Glenn ; et al. | 2012-10-11 |
Multi-core Microprocessor That Performs X86 Isa And Arm Isa Machine Language Program Instructions By Hardware Translation Into Microinstructions Executed By Common Execution Pipeline
App 20120260065 - Henry; G. Glenn ; et al. | 2012-10-11 |
Emulation Of Execution Mode Banked Registers
App 20120260073 - Henry; G. Glenn ; et al. | 2012-10-11 |
Heterogeneous Isa Microprocessor That Preserves Non-isa-specific Configuration State When Reset To Different Isa
App 20120260066 - Henry; G. Glenn ; et al. | 2012-10-11 |
Apparatus And Method For Handling Of Modified Immediate Constant During Instruction Translation
App 20120260068 - Henry; G. Glenn ; et al. | 2012-10-11 |
Load Multiple And Store Multiple Instructions In A Microprocessor That Emulates Banked Registers
App 20120260042 - Henry; G. Glenn ; et al. | 2012-10-11 |
Efficient Conditional Alu Instruction In Read-port Limited Register File Microprocessor
App 20120260074 - Henry; G. Glenn ; et al. | 2012-10-11 |
| 