Hendrickson; Olaf K.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Hendrickson; Olaf K..The latest application filed is for "implementing processor functional verification by generating and running constrained random irritator tests for multiple processor system and processor core with multiple threads".

Company Profile

0.6.8

Hendrickson; Olaf K. - Rochester MN

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Implementing random content of program loops in random test generation for processor verification Grant 10,061,672 - Dagan , et al. August 28, 2	2018-08-28
Implementing processor functional verification by generating and running constrained random irritator tests for multiple processor system and processor core with multiple threads Grant 9,734,033 - Hendrickson , et al. August 15, 2	2017-08-15
Implementing processor functional verification by generating and running constrained random irritator tests for multiple processor system and processor core with multiple threads Grant 9,720,793 - Hendrickson , et al. August 1, 2	2017-08-01
Implementing Processor Functional Verification By Generating And Running Constrained Random Irritator Tests For Multiple Processor System And Processor Core With Multiple Threads App 20160162381 - Hendrickson; Olaf K. ; et al.	2016-06-09
Implementing Processor Functional Verification By Generating And Running Constrained Random Irritator Tests For Multiple Processor System And Processor Core With Multiple Threads App 20160162380 - Hendrickson; Olaf K. ; et al.	2016-06-09
Implementing automated memory address recording in constrained random test generation for verification of processor hardware designs Grant 9,251,023 - Atherton , et al. February 2, 2	2016-02-02
Functional testing of a processor design Grant 8,918,678 - Almog , et al. December 23, 2	2014-12-23
Implementing Random Content Of Program Loops In Random Test Generation For Processor Verification App 20140257739 - Dagan; Adi ; et al.	2014-09-11
Implementing Automated Memory Address Recording In Constrained Random Test Generation For Verification Of Processor Hardware Designs App 20140257736 - Atherton; Craig T. ; et al.	2014-09-11
Functional Testing Of A Processor Design App 20140101628 - Almog; Eli ; et al.	2014-04-10
Functional Testing Of A Processor Design App 20130191689 - Almog; Eli ; et al.	2013-07-25
Software table walk during test verification of a simulated densely threaded network on a chip Grant 8,275,598 - Andreev , et al. September 25, 2	2012-09-25
Software Table Walk During Test Verification Of A Simulated Densely Threaded Network On A Chip App 20100223505 - ANDREEV; ANATOLI S. ; et al.	2010-09-02

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.