| Patent | Date |
|---|
Determining positions of storage elements in a logic design
Grant 9,858,380 - Helvey , et al. January 2, 2 | 2018-01-02 |
Method To Adjust Alley Gap Between Large Blocks For Floorplan Optimization
App 20170169155 - AMUNDSON; Michael D. ; et al. | 2017-06-15 |
Determining Positions Of Storage Elements In A Logic Design
App 20170083660 - Helvey; Timothy D. ; et al. | 2017-03-23 |
Implementing enhanced physical design quality using historical placement analytics
Grant 9,223,923 - Amundson , et al. December 29, 2 | 2015-12-29 |
Implementing enhanced physical design quality using historical placement analytics
Grant 9,218,445 - Amundson , et al. December 22, 2 | 2015-12-22 |
Implementing Enhanced Physical Design Quality Using Historical Placement Analytics
App 20150205899 - Amundson; Michael D. ; et al. | 2015-07-23 |
Implementing Enhanced Physical Design Quality Using Historical Placement Analytics
App 20150205900 - Amundson; Michael D. ; et al. | 2015-07-23 |
Implementing enhanced net routing congestion resolution of non-rectangular or rectangular hierarchical macros
Grant 9,087,172 - Ellavsky , et al. July 21, 2 | 2015-07-21 |
Implementing Enhanced Net Routing Congestion Resolution Of Non-rectangular Or Rectangular Hierarchical Macros
App 20150100937 - Ellavsky; Matthew R. ; et al. | 2015-04-09 |
Analyzing sparse wiring areas of an integrated circuit design
Grant 8,949,755 - Helvey February 3, 2 | 2015-02-03 |
Analyzing Sparse Wiring Areas Of An Integrated Circuit Design
App 20140331196 - Helvey; Timothy D. | 2014-11-06 |
Analyzing Timing Requirements Of A Hierarchical Integrated Circuit Design
App 20140282320 - Helvey; Timothy D. | 2014-09-18 |
Implementing Z directional macro port assignment
Grant 8,826,214 - Ellavsky , et al. September 2, 2 | 2014-09-02 |
Analyzing timing requirements of a hierarchical integrated circuit design
Grant 8,819,612 - Helvey August 26, 2 | 2014-08-26 |
Changing the location of a buffer bay in a netlist
Grant 8,689,170 - Ellavsky , et al. April 1, 2 | 2014-04-01 |
Swapping ports to change the timing window overlap of adjacent nets
Grant 8,631,370 - Benjamin , et al. January 14, 2 | 2014-01-14 |
Swapping Ports To Change The Timing Window Overlap Of Adjacent Nets
App 20130290921 - Benjamin; Samuel R. ; et al. | 2013-10-31 |
Implementing Z Directional Macro Port Assignment
App 20130198702 - Ellavsky; Matthew R. ; et al. | 2013-08-01 |
Changing The Location Of A Buffer Bay In A Netlist
App 20130174114 - Ellavsky; Matthew R. ; et al. | 2013-07-04 |
Slack-based timing budget apportionment
Grant 8,473,884 - Daede , et al. June 25, 2 | 2013-06-25 |
Implementing net routing with enhanced correlation of pre-buffered and post-buffered routes
Grant 8,448,123 - Curtis , et al. May 21, 2 | 2013-05-21 |
Implementing Z directional macro port assignment
Grant 8,448,121 - Ellavsky , et al. May 21, 2 | 2013-05-21 |
Changing the location of a buffer bay in a netlist
Grant 8,413,104 - Ellavsky , et al. April 2, 2 | 2013-04-02 |
Iimplementing Z Directional Macro Port Assignment
App 20130042214 - Ellavsky; Matthew R. ; et al. | 2013-02-14 |
Implementing timing pessimism reduction for parallel clock trees
Grant 8,316,333 - Darsow , et al. November 20, 2 | 2012-11-20 |
Changing The Location Of A Buffer Bay In A Netlist
App 20120290995 - Ellavsky; Matthew R. ; et al. | 2012-11-15 |
Slack-based Timing Budget Apportionment
App 20120284677 - Daede; Ronald J. ; et al. | 2012-11-08 |
Implementing forward tracing to reduce pessimism in static timing of logic blocks laid out in parallel structures on an integrated circuit chip
Grant 8,271,923 - Darsow , et al. September 18, 2 | 2012-09-18 |
Slack-based timing budget apportionment
Grant 8,250,509 - Daede , et al. August 21, 2 | 2012-08-21 |
Slack-based Timing Budget Apportionment
App 20120124537 - Daede; Ronald J. ; et al. | 2012-05-17 |
Implementing Net Routing With Enhanced Correlation Of Pre-buffered And Post-buffered Routes
App 20120102446 - Curtis; Paul G. ; et al. | 2012-04-26 |
Implementing Forward Tracing To Reduce Pessimism In Static Timing Of Logic Blocks Laid Out In Parallel Structures On An Integrated Circuit Chip
App 20120023466 - Darsow; Craig M. ; et al. | 2012-01-26 |
Implementing Timing Pessimism Reduction For Parallel Clock Trees
App 20120023469 - Darsow; Craig M. ; et al. | 2012-01-26 |
Replicating timing data in static timing analysis operation
Grant 8,024,683 - Darsow , et al. September 20, 2 | 2011-09-20 |
Concurrently modeling delays between points in static timing analysis operation
Grant 7,962,871 - Darsow , et al. June 14, 2 | 2011-06-14 |
Replicating Timing Data in Static Timing Analysis Operation
App 20090293031 - Darsow; Craig M. ; et al. | 2009-11-26 |
Concurrently Modeling Delays Between Points in Static Timing Analysis Operation
App 20090293030 - Darsow; Craig M. ; et al. | 2009-11-26 |
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