Heineck; Lars

Patent Applications and Registrations

Patent applications and USPTO patent grants for Heineck; Lars.The latest application filed is for "semiconductor devices".

Company Profile

3.27.32

Heineck; Lars - Hiroshima JP
Heineck; Lars - Garden City ID
Heineck; Lars - Radebeul DE
Heineck; Lars - Radebehl DE
Heineck; Lars - Dresden DE
Heineck; Lars - Paris FR

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Semiconductor devices Grant 10,566,332 - Wang , et al. Feb	2020-02-18
Semiconductor Devices App 20190088658 - Wang; Kuo-Chen ; et al.	2019-03-21
Methods for fabricating a semiconductor memory device Grant 10,163,909 - Wang , et al. Dec	2018-12-25
Semiconductor Memory Device Having Coplanar Digit Line Contacts And Storage Node Contacts In Memory Array And Method For Fabricating The Same App 20180102366 - Wang; Kuo-Chen ; et al.	2018-04-12
Semiconductor memory device having coplanar digit line contacts and storage node contacts in memory array and method for fabricating the same Grant 9,881,924 - Wang , et al. January 30, 2	2018-01-30
Semiconductor Memory Device Having Coplanar Digit Line Contacts And Storage Node Contacts In Memory Array And Method For Fabricating The Same App 20170330882 - Wang; Kuo-Chen ; et al.	2017-11-16
Silicon buried digit line access device and method of forming the same Grant 9,691,773 - Surthi , et al. June 27, 2	2017-06-27
Memory cells, arrays of memory cells, and methods of forming memory cells Grant 9,337,201 - Heineck , et al. May 10, 2	2016-05-10
Method of forming buried word line structure Grant 9,263,317 - Park , et al. February 16, 2	2016-02-16
Buried digitline (BDL) access device and memory array Grant 9,070,584 - Surthi , et al. June 30, 2	2015-06-30
Silicon Buried Digit Line Access Device And Method Of Forming The Same App 20150123280 - Surthi; Shyam ; et al.	2015-05-07
Method for semiconductor cross pitch doubled patterning process Grant 9,012,330 - Nair , et al. April 21, 2	2015-04-21
Method For Semiconductor Cross Pitch Doubled Patterning Process App 20150056810 - Nair; Vinay ; et al.	2015-02-26
Buried Digitline (bdl) Access Device And Memory Array App 20140346652 - Surthi; Shyam ; et al.	2014-11-27
Method Of Forming Buried Word Line Structure App 20140213035 - Park; Inho ; et al.	2014-07-31
Buried Word Line Structure And Method Of Forming The Same App 20140159140 - Park; Inho ; et al.	2014-06-12
Buried word line structure and method of forming the same Grant 8,735,267 - Park , et al. May 27, 2	2014-05-27
Dram Structure With Buried Word Lines And Fabrication Thereof, And Ic Structure And Fabrication Thereof App 20140042548 - Liu; Hao-Chieh ; et al.	2014-02-13
Semiconductor process and semiconductor structure for memory array with buried digit lines (BDL) Grant 8,502,294 - Surthi , et al. August 6, 2	2013-08-06
Method of fabricating a cell contact and a digit line for a semiconductor device Grant 8,450,207 - Surthi , et al. May 28, 2	2013-05-28
Memory cells, arrays of memory cells, and methods of forming memory cells Grant 8,361,856 - Heineck , et al. January 29, 2	2013-01-29
Memory Cells, Arrays Of Memory Cells, And Methods Of Forming Memory Cells App 20130001666 - Heineck; Lars ; et al.	2013-01-03
Method Of Fabricating A Cell Contact And A Digit Line For A Semiconductor Device App 20120329274 - Surthi; Shyam ; et al.	2012-12-27
Dram Structure With Buried Word Lines And Fabrication Thereof, And Ic Structure And Fabrication Thereof App 20120292716 - Liu; Hao-Chieh ; et al.	2012-11-22
Memory Cells, Arrays Of Memory Cells, And Methods Of Forming Memory Cells App 20120104491 - Heineck; Lars ; et al.	2012-05-03
Interconnect structure for semiconductor devices Grant 8,138,538 - Moll , et al. March 20, 2	2012-03-20
Word line to bit line spacing method and apparatus Grant 7,838,928 - Graf , et al. November 23, 2	2010-11-23
Single-Sided Trench Contact Window App 20100090348 - Park; Inho ; et al.	2010-04-15
Interconnect Structure For Semiconductor Devices App 20100090264 - Moll; Hans-Peter ; et al.	2010-04-15
Word Line to Bit Line Spacing Method and Apparatus App 20090302380 - Graf; Werner ; et al.	2009-12-10
Method for forming an integrated circuit having an active semiconductor device and integrated circuit App 20080315326 - Graf; Werner ; et al.	2008-12-25
Manufacturing method for forming a recessed channel transistor, method for forming a corresponding integrated semiconductor memory device and corresponding self-aligned mask structure App 20080299722 - Hartwich; Jessica ; et al.	2008-12-04
Memory Cell Array And Method Of Forming The Memory Cell Array App 20080061340 - Heineck; Lars ; et al.	2008-03-13
Method for producing a semiconductor structure Grant 7,314,803 - Graf , et al. January 1, 2	2008-01-01
Integrated Circuit Including a Memory Cell Array App 20070290249 - Popp; Martin ; et al.	2007-12-20
Memory cell array and method of forming the same Grant 7,274,060 - Popp , et al. September 25, 2	2007-09-25
Manufacturing method for an integrated semiconductor structure and corresponding integrated semiconductor structure App 20070077720 - Heineck; Lars ; et al.	2007-04-05
Connecting structure and method for manufacturing the same App 20070032032 - Heineck; Lars ; et al.	2007-02-08
Connecting structure and method for manufacturing the same App 20070032033 - Heineck; Lars ; et al.	2007-02-08
Memory cell array and method of forming the same App 20060284225 - Popp; Martin ; et al.	2006-12-21
Method for production of contacts on a wafer App 20060276019 - Graf; Werner ; et al.	2006-12-07
Method for production of contacts on a wafer Grant 7,094,674 - Graf , et al. August 22, 2	2006-08-22
Method for fabricating transistors of different conduction types and having different packing densities in a semiconductor substrate Grant 7,087,492 - Popp , et al. August 8, 2	2006-08-08
Method for producing a semiconductor structure App 20060141756 - Graf; Werner ; et al.	2006-06-29
Method for fabricating a contact hole plane in a memory module Grant 7,018,781 - Frohlich , et al. March 28, 2	2006-03-28
Semiconductor trench structure Grant 6,919,255 - Birner , et al. July 19, 2	2005-07-19
Method for fabricating a trench capacitor with an insulation collar Grant 6,916,721 - Heineck , et al. July 12, 2	2005-07-12
Method for fabricating transistors of different conduction types and having different packing densities in a semiconductor substrate App 20050026373 - Popp, Martin ; et al.	2005-02-03
Method for fabricating a contact hole plane in a memory module App 20050003308 - Frohlich, Hans-Georg ; et al.	2005-01-06
Method for fabricating a trench capacitor with an insulation collar App 20040197988 - Heineck, Lars ; et al.	2004-10-07
Method for production of contacts on a wafer App 20040142548 - Graf, Werner ; et al.	2004-07-22
Semiconductor trench structure App 20040126961 - Birner, Albert ; et al.	2004-07-01
Method of fabricating a Si3N4/polycide structure using a dielectric sacrificial layer as a mask Grant 6,342,452 - Coronel , et al. January 29, 2	2002-01-29

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.