Heile; Francis B

Patent Applications and Registrations

Patent applications and USPTO patent grants for Heile; Francis B.The latest application filed is for "programmable logic array integrated circuits".

Company Profile

0.32.5

Heile; Francis B - Santa Clara CA
Heile; Francis B. - Santa Clara CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
PCI-compatible programmable logic devices Grant 7,148,722 - Cliff , et al. December 12, 2	2006-12-12
Programmable logic array integrated circuit devices Grant 6,815,981 - Cliff , et al. November 9, 2	2004-11-09
Programmable logic array integrated circuits Grant 6,759,870 - Cliff , et al. July 6, 2	2004-07-06
PCI-compatible programmable logic devices Grant 6,646,467 - Cliff , et al. November 11, 2	2003-11-11
Programmable logic array integrated circuit devices App 20030128051 - Cliff, Richard G. ; et al.	2003-07-10
Programmable logic array integrated circuits App 20030128052 - Cliff, Richard G. ; et al.	2003-07-10
Programmable logic array integrated circuit devices App 20030016053 - Cliff, Richard G. ; et al.	2003-01-23
Generation of sub-netlists for use in incremental compilation Grant 6,490,717 - Pedersen , et al. December 3, 2	2002-12-03
Content addressable memory encoded outputs Grant 6,453,382 - Heile September 17, 2	2002-09-17
Programmable logic array integrated circuit devices Grant 6,392,438 - Cliff , et al. May 21, 2	2002-05-21
Programmable logic array device with random access memory configurable as product terms App 20020057621 - Heile, Francis B.	2002-05-16
Programmable logic devices with improved content addressable memory capabilities Grant 6,344,989 - Heile February 5, 2	2002-02-05
Programmable logic architecture incorporating a content addressable embedded array block Grant 6,326,807 - Veenstra , et al. December 4, 2	2001-12-04
Interface for compiling project variations in electronic design environments Grant 6,321,369 - Heile , et al. November 20, 2	2001-11-20
Electronic design automation tool for display of design profile Grant 6,317,860 - Heile November 13, 2	2001-11-13
Incremental compilation of electronic design for work group Grant 6,298,319 - Heile , et al. October 2, 2	2001-10-02
Programmable logic array integrated circuit architectures App 20010022519 - Cliff, Richard G. ; et al.	2001-09-20
Mapping heterogeneous logic elements in a programmable logic device Grant 6,195,788 - Leaver , et al. February 27, 2	2001-02-27
Programmable logic architecture incorporating a content addressable embedded array block Grant 6,160,419 - Veenstra , et al. December 12, 2	2000-12-12
Programmable logic devices with improved content addressable memory capabilities Grant 6,144,573 - Heile November 7, 2	2000-11-07
Generation of sub-netlists for use in incremental compilation Grant 6,134,705 - Pedersen , et al. October 17, 2	2000-10-17
Local compilation in context within a design hierarchy Grant 6,026,226 - Heile , et al. February 15, 2	2000-02-15
Programmable logic array device with random access memory configurable as product terms Grant 6,020,759 - Heile February 1, 2	2000-02-01
Logic region resources for programmable logic devices Grant 5,999,015 - Cliff , et al. December 7, 1	1999-12-07
Work group computing for electronic design automation Grant 5,983,277 - Heile , et al. November 9, 1	1999-11-09
Programmable logic array integrated circuit architectures Grant 5,963,049 - Cliff , et al. October 5, 1	1999-10-05
Programmable logic array integrated circuit devices with interleaved logic array blocks Grant 5,909,126 - Cliff , et al. June 1, 1	1999-06-01
Programmable logic array integrated circuit devices Grant 5,850,152 - Cliff , et al. December 15, 1	1998-12-15
Programmable logic array intergrated circuit devices Grant 5,850,151 - Cliff , et al. December 15, 1	1998-12-15
Routing connections for programmable logic array integrated circuits Grant 5,670,895 - Kazarian , et al. September 23, 1	1997-09-23
Programmable logic array with local and global conductors Grant 5,485,103 - Pedersen , et al. January 16, 1	1996-01-16
High-density erasable programmable logic device architecture using multiplexer interconnections Grant 5,384,499 - Pedersen , et al. January 24, 1	1995-01-24
Programmable logic device with multiplexer-based programmable interconnections Grant 5,376,844 - Pedersen , et al. * December 27, 1	1994-12-27
High-density erasable programmable logic device architecture using multiplexer interconnections Grant 5,268,598 - Pedersen , et al. December 7, 1	1993-12-07
Programmable logic element interconnections for programmable logic array integrated circuits Grant 5,260,610 - Pedersen , et al. November 9, 1	1993-11-09
Programmable logic array having local and long distance conductors Grant 5,260,611 - Cliff , et al. November 9, 1	1993-11-09
High-density erasable programmable logic device architecture using multiplexer interconnections Grant 5,241,224 - Pedersen , et al. August 31, 1	1993-08-31

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