Heightley; John D.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Heightley; John D..The latest application filed is for "configurable architecture hybrid analog/digital delay locked loop (dll) and technique with fast open loop digital locking for integrated circuit devices".

Company Profile

0.11.9

Heightley; John D. - Colorado Springs CO
Heightley; John D. - Monumet CO
Heightley; John D. - Monument CO
Heightley; John D. - Basking Ridge NJ

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Configurable architecture hybrid analog/digital delay locked loop (DLL) and technique with fast open loop digital locking for integrated circuit devices Grant 7,876,137 - Heightley January 25, 2	2011-01-25
Configurable Architecture Hybrid Analog/digital Delay Locked Loop (dll) And Technique With Fast Open Loop Digital Locking For Integrated Circuit Devices App 20100123494 - Heightley; John D.	2010-05-20
Circuit and technique for adjusting and accurately controlling clock duty cycles in integrated circuit devices Grant 7,518,425 - Heightley April 14, 2	2009-04-14
Use of multiple voltage controlled delay lines for precise alignment and duty cycle control of the data output of a DDR memory device Grant 7,474,136 - Heightley January 6, 2	2009-01-06
Use Of Multiple Voltage Controlled Delay Lines For Precise Alignment And Duty Cycle Control Of The Data Output Of A Ddr Memory Device App 20080278211 - Heightley; John D.	2008-11-13
Circuit And Technique For Adjusting And Accurately Controlling Clock Duty Cycles In Integrated Circuit Devices App 20080186068 - Heightley; John D.	2008-08-07
Dual equalization devices for long data line pairs Grant 7,218,564 - Faue , et al. May 15, 2	2007-05-15
System and method for controlling the drive strength of output drivers in integrated circuit devices App 20070103124 - Heightley; John D.	2007-05-10
Method for improving the timing resolution of DLL controlled delay lines App 20070096787 - Heightley; John D.	2007-05-03
Low voltage differential amplifier circuit for wide voltage range operation Grant 7,167,052 - Heightley , et al. January 23, 2	2007-01-23
Low voltage differential amplifier circuit and a sampled low power bias control technique enabling accommodation of an increased range of input levels Grant 7,102,439 - Heightley , et al. September 5, 2	2006-09-05
Voltage-controlled analog delay locked loop Grant 7,071,745 - Heightley , et al. July 4, 2	2006-07-04
Dual equalization devices for long data line pairs App 20060023529 - Faue; Jon Allan ; et al.	2006-02-02
Low Voltage Differential Amplifier Circuit And A Sampled Low Power Bias Control Technique Enabling Accommodation Of An Increased Range Of Input Levels App 20050275462 - Heightley, John D. ; et al.	2005-12-15
Low voltage differential amplifier circuit for wide voltage range operation App 20050275461 - Heightley, John D. ; et al.	2005-12-15
Voltage-controlled analog delay locked loop App 20050174155 - Heightley, John D. ; et al.	2005-08-11
Dummy cell arrangement for an MOS memory Grant 4,363,111 - Heightley , et al. December 7, 1	1982-12-07
Asynchronously equillibrated and pre-charged static ram Grant 4,355,377 - Sud , et al. October 19, 1	1982-10-19
Shift Register Employing Two-phase Coupling And Transient Storage Between Stages Grant 3,614,469 - Heightley October 19, 1	1971-10-19
Threshold Logic Gate Grant 3,597,626 - Heightley August 3, 1	1971-08-03

Company Registrations

SEC

0001184423

HEIGHTLEY JOHN D

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