Heidel; David F.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Heidel; David F..The latest application filed is for "method and structure to reduce soft error rate susceptibility in semiconductor structures".

Company Profile

0.9.5

Heidel; David F. - Mahopac NY US

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
In-line stacking of transistors for soft error rate hardening Grant 9,165,917 - Cannon , et al. October 20, 2	2015-10-20
Detecting chip alterations with light emission Grant 9,075,106 - Bernstein , et al. July 7, 2	2015-07-07
Method and structure to reduce soft error rate susceptibility in semiconductor structures Grant 8,362,600 - Cabral, Jr. , et al. January 29, 2	2013-01-29
Method And Structure To Reduce Soft Error Rate Susceptibility In Semiconductor Structures App 20110175211 - Cabral, JR.; Cyril ; et al.	2011-07-21
Detecting Chip Alterations with Light Emission App 20110026806 - Bernstein; Kerry ; et al.	2011-02-03
In-line Stacking Of Transistors For Soft Error Rate Hardening App 20100301446 - Cannon; Ethan H. ; et al.	2010-12-02
On-chip jitter measurement circuit Grant 7,791,330 - Heidel , et al. September 7, 2	2010-09-07
On-chip Jitter Measurement Circuit App 20080284477 - Heidel; David F. ; et al.	2008-11-20
On-chip jitter measurement circuit Grant 7,439,724 - Heidel , et al. October 21, 2	2008-10-21
System and method for accelerated detection of transient particle induced soft error rates in integrated circuits Grant 7,084,660 - Ackaret , et al. August 1, 2	2006-08-01
On-chip jitter measurement circuit App 20050036578 - Heidel, David F. ; et al.	2005-02-17

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