loadpatents
Patent applications and USPTO patent grants for Hedinger; Peter.The latest application filed is for "processing system".
Patent | Date |
---|---|
Processing system with a main processor pipeline and a co-processor pipeline Grant 11,256,516 - Muller , et al. February 22, 2 | 2022-02-22 |
Processing System App 20210109760 - MULLER; Henk Lambertus ;   et al. | 2021-04-15 |
Synchronising groups of threads with dedicated hardware logic Grant 8,966,488 - May , et al. February 24, 2 | 2015-02-24 |
Thread communications Grant 8,347,312 - May , et al. January 1, 2 | 2013-01-01 |
Scheduling thread upon ready signal set when port transfers data on trigger time activation Grant 7,617,386 - May , et al. November 10, 2 | 2009-11-10 |
Resuming thread to service ready port transferring data externally at different clock rate than internal circuitry of a processor Grant 7,613,909 - May , et al. November 3, 2 | 2009-11-03 |
Synchronisation App 20090013323 - May; Michael David ;   et al. | 2009-01-08 |
Thread Communications App 20090013329 - May; Michael David ;   et al. | 2009-01-08 |
Clocked ports App 20080263330 - May; Michael David ;   et al. | 2008-10-23 |
Timed ports App 20080263318 - May; Michael David ;   et al. | 2008-10-23 |
Code generation Grant 7,216,342 - Southwell , et al. May 8, 2 | 2007-05-08 |
Processor and a method for handling and encoding no-operation instructions Grant 7,062,634 - Southwell , et al. June 13, 2 | 2006-06-13 |
Pseudo register file write ports App 20050278510 - Jacobs, Kristen ;   et al. | 2005-12-15 |
Cache memory operation Grant 6,959,363 - Southwell , et al. October 25, 2 | 2005-10-25 |
Evaluation and optimization of code Grant 6,883,067 - Southwell , et al. April 19, 2 | 2005-04-19 |
Cache memory operation App 20040030839 - Southwell, Trefor ;   et al. | 2004-02-12 |
Code generation App 20030177483 - Southwell, Trefor ;   et al. | 2003-09-18 |
Evaluation and optimisation of code App 20030154342 - Southwell, Trefor ;   et al. | 2003-08-14 |
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