Healy; Michael B.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Healy; Michael B..The latest application filed is for "multi-tag storage techniques for efficient data compression in caches".

Company Profile

10.42.39

Healy; Michael B. - Cortlandt Manor NY
Healy; Michael B. - White Plains NY

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Servicing indirect data storage requests with multiple memory controllers Grant 11,210,092 - Emma , et al. December 28, 2	2021-12-28
Systems, methods and computer program products using multi-tag storage for efficient data compression in caches Grant 10,831,669 - Nair , et al. November 10, 2	2020-11-10
Aggregating, disaggregating and converting electronic transaction request messages Grant 10,776,155 - Emma , et al. Sept	2020-09-15
Latency-agnostic memory controller Grant 10,740,003 - Emma , et al. A	2020-08-11
Multi-tag Storage Techniques For Efficient Data Compression In Caches App 20200174939 - Nair; Prashant Jayaprakash ; et al.	2020-06-04
Partitioned memory with locally aggregated copy pools Grant 10,613,774 - Emma , et al.	2020-04-07
Partitioned memory with locally aggregated copy pools Grant 10,606,487 - Emma , et al.	2020-03-31
Latency-agnostic Memory Controller App 20190294342 - Emma; Philip G. ; et al.	2019-09-26
Aggregating, Disaggregating And Converting Electronic Transaction Request Messages App 20190286473 - Emma; Philip G. ; et al.	2019-09-19
Servicing Indirect Storage Requests App 20190278601 - Emma; Philip G. ; et al.	2019-09-12
Built-in self-test for embedded spin-transfer torque magnetic random access memory Grant 10,283,212 - Healy , et al.	2019-05-07
Partitioned Memory With Locally Aggregated Copy Pools App 20180267725 - Emma; Philip G. ; et al.	2018-09-20
Partitioned Memory With Locally Aggregated Copy Pools App 20180267722 - Emma; Philip G. ; et al.	2018-09-20
Memory system with switchable operating bands Grant 10,067,702 - Healy , et al. September 4, 2	2018-09-04
Extended error correction coding data storage Grant 10,063,263 - Healy , et al. August 28, 2	2018-08-28
Extended error correction coding data storage Grant 10,027,349 - Healy , et al. July 17, 2	2018-07-17
Error monitoring of a memory device containing embedded error correction Grant 10,019,312 - Healy , et al. July 10, 2	2018-07-10
Built-in Self-test For Embedded Spin-transfer Torque Magnetic Random Access Memory App 20180151246 - Healy; Michael B. ; et al.	2018-05-31
Detecting a cryogenic attack on a memory device with embedded error correction Grant 9,940,457 - Healy , et al. April 10, 2	2018-04-10
Memory System With Switchable Operating Bands App 20180074739 - Healy; Michael B. ; et al.	2018-03-15
Memory system with switchable operating bands Grant 9,898,218 - Healy , et al. February 20, 2	2018-02-20
Thermal-aware memory Grant 9,761,294 - Healy , et al. September 12, 2	2017-09-12
Error monitoring of a memory device containing embedded error correction Grant 9,747,148 - Healy , et al. August 29, 2	2017-08-29
Error Monitoring Of A Memory Device Containing Embedded Error Correction App 20170235632 - Healy; Michael B. ; et al.	2017-08-17
Error vector readout from a memory device Grant 9,734,008 - Healy , et al. August 15, 2	2017-08-15
Thermal-aware memory Grant 9,734,885 - Healy , et al. August 15, 2	2017-08-15
Error vector readout from a memory device Grant 9,733,870 - Healy , et al. August 15, 2	2017-08-15
Memory System With Switchable Operating Bands App 20170228186 - Healy; Michael B. ; et al.	2017-08-10
Three-dimensional processing system having at least one layer with circuitry dedicated to scan testing and system state checkpointing of other system layers Grant 9,696,379 - Buyuktosunoglu , et al. July 4, 2	2017-07-04
Memory device error history bit Grant 9,690,649 - Healy , et al. June 27, 2	2017-06-27
Selective memory error reporting Grant 9,684,555 - Healy , et al. June 20, 2	2017-06-20
Error Monitoring Of A Memory Device Containing Embedded Error Correction App 20170123882 - Healy; Michael B. ; et al.	2017-05-04
Memory device error history bit Grant 9,626,242 - Healy , et al. April 18, 2	2017-04-18
Error monitoring of a memory device containing embedded error correction Grant 9,606,851 - Healy , et al. March 28, 2	2017-03-28
Selective Memory Error Reporting App 20170060657 - Healy; Michael B. ; et al.	2017-03-02
3-D stacked multiprocessor structure with vertically aligned identical layout operating processors in independent mode or in sharing mode running faster components Grant 9,569,402 - Buyuktosunoglu , et al. February 14, 2	2017-02-14
Extended Error Correction Coding Data Storage App 20160342469 - Healy; Michael B. ; et al.	2016-11-24
Extended Error Correction Coding Data Storage App 20160342473 - Healy; Michael B. ; et al.	2016-11-24
Memory Device Error History Bit App 20160328284 - Healy; Michael B. ; et al.	2016-11-10
Error Vector Readout From A Memory Device App 20160328285 - Healy; Michael B. ; et al.	2016-11-10
Error Vector Readout From A Memory Device App 20160328290 - Healy; Michael B. ; et al.	2016-11-10
Memory Device Error History Bit App 20160328291 - Healy; Michael B. ; et al.	2016-11-10
Selective memory error reporting Grant 9,471,423 - Healy , et al. October 18, 2	2016-10-18
3-D stacked multiprocessor structures and methods for multimodal operation of same Grant 9,471,535 - Buyuktosunoglu , et al. October 18, 2	2016-10-18
3-D stacked multiprocessor structures and methods for multimodal operation of same Grant 9,442,884 - Buyuktosunoglu , et al. September 13, 2	2016-09-13
Detecting A Cryogenic Attack On A Memory Device With Embedded Error Correction App 20160239663 - Healy; Michael B. ; et al.	2016-08-18
Error Monitoring Of A Memory Device Containing Embedded Error Correction App 20160224412 - Healy; Michael B. ; et al.	2016-08-04
Three-dimensional Processing System Having At Least One Layer With Circuitry Dedicated To Scan Testing And System State Checkpointing Of Other System Layers App 20160209470 - Buyuktosunoglu; Alper ; et al.	2016-07-21
Three-dimensional processing system having independent calibration and statistical collection layer Grant 9,389,876 - Emma , et al. July 12, 2	2016-07-12
Three-dimensional processing system having at least one layer with circuitry dedicated to scan testing and system state checkpointing of other system layers Grant 9,383,411 - Buyuktosunoglu , et al. July 5, 2	2016-07-05
Three-dimensional processing system having multiple caches that can be partitioned, conjoined, and managed according to more than one set of rules and/or configurations Grant 9,336,144 - Buyuktosunoglu , et al. May 10, 2	2016-05-10
3-D stacked multiprocessor structure with vertically aligned identical layout operating processors in independent mode or in sharing mode running faster components Grant 9,298,672 - Buyuktosunoglu , et al. March 29, 2	2016-03-29
Memory architectures having wiring structures that enable different access patterns in multiple dimensions Grant 9,257,152 - Buyuktosunoglu , et al. February 9, 2	2016-02-09
Three-dimensional computer processor systems having multiple local power and cooling layers and a global interconnection structure Grant 9,195,630 - Buyuktosunoglu , et al. November 24, 2	2015-11-24
Memory architectures having wiring structures that enable different access patterns in multiple dimensions Grant 9,190,118 - Buyuktosunoglu , et al. November 17, 2	2015-11-17
Three-dimensional Processing System Having Independent Calibration And Statistical Collection Layer App 20150121052 - Emma; Philip G. ; et al.	2015-04-30
Three-dimensional Processing System Having Multiple Caches That Can Be Partitioned, Conjoined, And Managed According To More Than One Set Of Rules And/or Configurations App 20150032962 - Buyuktosunoglu; Alper ; et al.	2015-01-29
Three-dimensional Processing System Having At Least One Layer With Circuitry Dedicated To Scan Testing And System State Checkpointing Of Other System Layers App 20150006986 - Buyuktosunoglu; Alper ; et al.	2015-01-01
Three-dimensional Computer Processor Systems Having Multiple Local Power And Cooling Layers And A Global Interconnection Structure App 20140281378 - Buyuktosunoglu; Alper ; et al.	2014-09-18
3-D stacked multiprocessor structures and methods to enable reliable operation of processors at speeds above specified limits Grant 8,826,073 - Buyuktosunoglu , et al. September 2, 2	2014-09-02
3-D stacked multiprocessor structures and methods to enable reliable operation of processors at speeds above specified limits Grant 8,799,710 - Buyuktosunoglu , et al. August 5, 2	2014-08-05
Memory Architectures Having Wiring Structures That Enable Different Access Patterns In Multiple Dimensions App 20140133209 - Buyuktosunoglu; Alper ; et al.	2014-05-15
Memory Architectures Having Wiring Structures That Enable Different Access Patterns In Multiple Dimensions App 20140133208 - Buyuktosunoglu; Alper ; et al.	2014-05-15
3-d Stacked Multiprocessor Structures And Methods To Enable Reliable Operation Of Processors At Speeds Above Specified Limits App 20140006852 - Buyuktosunoglu; Alper ; et al.	2014-01-02
3-d Stacked Multiprocessor Structures And Methods To Enable Reliable Operation Of Processors At Speeds Above Specified Limits App 20140006750 - Buyuktosunoglu; Alper ; et al.	2014-01-02
3-d Stacked Multiprocessor Structures And Methods For Multimodal Operation Of Same App 20130283006 - Buyuktosunoglu; Alper ; et al.	2013-10-24
3-d Stacked Multiprocessor Structures And Methods For Multimodal Operation Of Same App 20130283009 - Buyuktosunoglu; Alper ; et al.	2013-10-24
3-d Stacked Multiprocessor Structures And Methods For Multimodal Operation Of Same App 20130283008 - Buyuktosunoglu; Alper ; et al.	2013-10-24
3-d Stacked Multiprocessor Structures And Methods For Multimodal Operation Of Same App 20130283010 - Buyuktosunoglu; Alper ; et al.	2013-10-24

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.