He; Yue-Song

Patent Applications and Registrations

Patent applications and USPTO patent grants for He; Yue-Song.The latest application filed is for "methods and circuitry for programming non-volatile resistive switches using varistors".

Company Profile

4.45.24

He; Yue-Song - San Jose CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Methods And Circuitry For Programming Non-volatile Resistive Switches Using Varistors App 20200075088 - He; Yue-Song ; et al.	2020-03-05
Methods and circuitry for programming non-volatile resistive switches using varistors Grant 10,573,375 - He , et al. Feb	2020-02-25
Integrated circuits with programmable non-volatile resistive switch elements Grant 10,447,275 - Lee , et al. Oc	2019-10-15
Integrated circuits with complementary non-volatile resistive memory elements Grant 10,269,426 - Smolen , et al.	2019-04-23
Integrated Circuits With Programmable Non-volatile Resistive Switch Elements App 20190020344 - Lee; Andy L. ; et al.	2019-01-17
Integrated Circuits With Complementary Non-volatile Resistive Memory Elements App 20180366192 - Smolen; Richard G. ; et al.	2018-12-20
Integrated circuits with programmable non-volatile resistive switch elements Grant 10,090,840 - Lee , et al. October 2, 2	2018-10-02
Parallel Configured Resistive Memory Elements App 20170365643 - McElheny; Peter John ; et al.	2017-12-21
Techniques for enabling and disabling transistor legs in an output driver circuit Grant 9,793,888 - Tan , et al. October 17, 2	2017-10-17
Techniques For Enabling And Disabling Transistor Legs In An Output Driver Circuit App 20170264283 - Tan; Tat Hin ; et al.	2017-09-14
Apparatus and method for source side implantation after spacer formation to reduce short channel effects in metal oxide semiconductor field effect transistors Grant 8,896,048 - Fastow , et al. November 25, 2	2014-11-25
Heterojunction Oxide Memory Device With Barrier Layer App 20140001429 - He; Yue-Song ; et al.	2014-01-02
One-time Programmable Memory And Method For Making The Same App 20130161761 - Luan; Harry S. ; et al.	2013-06-27
One-time programmable memory and method for making the same Grant 8,330,189 - Luan , et al. December 11, 2	2012-12-11
Non-volatile memory devices with charge storage regions Grant 8,125,020 - He , et al. February 28, 2	2012-02-28
One-time Programmable Memory And Method For Making The Same App 20110309421 - Luan; Harry S. ; et al.	2011-12-22
Nonvolatile Memories With Laterally Recessed Charge-trapping Dielectric App 20100323511 - He; Yue-Song ; et al.	2010-12-23
Nonvolatile memories with laterally recessed charge-trapping dielectric Grant 7,816,726 - He , et al. October 19, 2	2010-10-19
Integrated circuits with substrate protrusions, including (but not limited to) floating gate memories Grant 7,808,032 - He , et al. October 5, 2	2010-10-05
Nonvolatile Memory With Floating Gates With Upward Protrusions App 20090321806 - Mei; Len ; et al.	2009-12-31
Method For Making Very Small Isolated Dots On Substrates App 20090256221 - Mei; Len ; et al.	2009-10-15
Nonvolatile Memory Arrays With Charge Trapping Dielectric And With Non-dielectric Nanodots App 20090251972 - He; Yue-Song ; et al.	2009-10-08
Split-gate non-volatile memory devices having nitride tunneling layers App 20090184359 - He; Yue-Song ; et al.	2009-07-23
Nonvolatile Memories With Laterally Recessed Charge-trapping Dielectric App 20090159957 - He; Yue-Song ; et al.	2009-06-25
Memory Devices With Split Gate And Blocking Layer App 20090101961 - He; Yue-Song ; et al.	2009-04-23
Non-volatile Memory Devices With Charge Storage Regions App 20090096013 - He; Yue-Song ; et al.	2009-04-16
NAND-type Flash Array with Reduced Inter-cell Coupling Resistance App 20090085069 - MEI; Len ; et al.	2009-04-02
Nonvolatile memory cell with multiple floating gates and a connection region in the channel Grant 7,511,333 - He , et al. March 31, 2	2009-03-31
Source Biasing Of Nor-type Flash Array With Dynamically Variable Source Resistance App 20080291723 - Wang; Daniel C. ; et al.	2008-11-27
Integrated circuits with substrate protrusions, including (but not limited to) floating gate memories Grant 7,452,776 - He , et al. November 18, 2	2008-11-18
Integrated Circuits With Substrate Protrusions, Including (but Not Limited To) Floating Gate Memories App 20080265305 - He; Yue-Song ; et al.	2008-10-30
Integrated Circuits With Substrate Protrusions, Including (but Not Limited To) Floating Gate Memories App 20080266949 - He; Yue-Song ; et al.	2008-10-30
Flash memory with high-K dielectric material between substrate and gate Grant 7,414,281 - Fastow , et al. August 19, 2	2008-08-19
Method for minimizing false detection of states in flash memory devices Grant 7,283,398 - He , et al. October 16, 2	2007-10-16
Nonvolatile memory cell with multiple floating gates and a connection region in the channel App 20070120171 - He; Yue-Song ; et al.	2007-05-31
Method for providing short channel effect control using a silicide VSS line Grant 7,109,555 - He September 19, 2	2006-09-19
Semiconductor device having triple LDD structure and lower gate resistance formed with a single implant process Grant 7,084,458 - Khan , et al. August 1, 2	2006-08-01
Methods and systems for reducing erase times in flash memory devices Grant 7,079,424 - Lee , et al. July 18, 2	2006-07-18
Ramped soft programming for control of erase voltage distributions in flash memory devices Grant 7,020,021 - Leung , et al. March 28, 2	2006-03-28
Flash memory device and a method of fabrication thereof Grant 6,979,619 - Fang , et al. December 27, 2	2005-12-27
Circuit and technique for accurately sensing low voltage flash memory devices Grant 6,963,506 - Wang , et al. November 8, 2	2005-11-08
Memory array with memory cells having reduced short channel effects Grant 6,963,106 - Fastow , et al. November 8, 2	2005-11-08
Reduced silicon gouging and common source line resistance in semiconductor devices Grant 6,953,752 - He , et al. October 11, 2	2005-10-11
Method for fabricating a flash memory device Grant 6,939,766 - He , et al. September 6, 2	2005-09-06
Method of fabricating semiconductor device having triple LDD structure and lower gate resistance formed with a single implant process Grant 6,939,770 - Khan , et al. September 6, 2	2005-09-06
Efficient and accurate sensing circuit and technique for low voltage flash memory devices Grant 6,898,124 - Wang , et al. May 24, 2	2005-05-24
N-Gate/N-Substrate or P-Gate/P-Substrate capacitor to characterize polysilicon gate depletion evaluation Grant 6,888,157 - Wang , et al. May 3, 2	2005-05-03
Method and system for improving short channel effect on a floating gate device Grant 6,878,589 - He , et al. April 12, 2	2005-04-12
Nitrogen oxidation to reduce encroachment Grant 6,867,119 - He , et al. March 15, 2	2005-03-15
Two-step source side implant for improving source resistance and short channel effect in deep sub-0.18.mu.m flash memory technology Grant 6,852,594 - Wang , et al. February 8, 2	2005-02-08
Method for reducing drain induced barrier lowering in a memory device Grant 6,833,297 - Fastow , et al. December 21, 2	2004-12-21
Structure for increasing drive current in a memory array and related method Grant 6,825,526 - He , et al. November 30, 2	2004-11-30
Method for reducing short channel effects in memory cells and related structure Grant 6,773,990 - Fastow , et al. August 10, 2	2004-08-10
Nitrogen oxidation to reduce encroachment App 20040084711 - He, Yue-Song ; et al.	2004-05-06
Performance in flash memory devices Grant 6,723,638 - He , et al. April 20, 2	2004-04-20
Virtual ground silicide bit line process for floating gate flash memory Grant 6,716,698 - He , et al. April 6, 2	2004-04-06
Reduction of sector connecting line capacitance using staggered metal lines Grant 6,700,201 - Fastow , et al. March 2, 2	2004-03-02
Source side boron implant and drain side MDD implant for deep sub 0.18 micron flash memory Grant 6,653,189 - Haddad , et al. November 25, 2	2003-11-25
Method and system for eliminating post etch residues Grant 6,647,995 - Huang , et al. November 18, 2	2003-11-18
Use of high-K dielectric material for ONO and tunnel oxide to improve floating gate flash memory coupling Grant 6,617,639 - Wang , et al. September 9, 2	2003-09-09
2Bit/cell architecture for floating gate flash memory product and associated method Grant 6,570,211 - He , et al. May 27, 2	2003-05-27
Low Defect Density Process For Deep Sub-0.18mum Flash Memory Technologies App 20030022440 - Wang, Zhigang ; et al.	2003-01-30
Re-oxidation approach to improve peripheral gate oxide integrity in a tunnel nitride oxidation process Grant 6,436,778 - Fang , et al. August 20, 2	2002-08-20
Lowered channel doping with source side boron implant for deep sub 0.18 micron flash memory cell App 20020106852 - He, Yue-Song ; et al.	2002-08-08
Process to improve read disturb for NAND flash memory devices Grant 6,380,033 - He , et al. April 30, 2	2002-04-30
Double layer hard mask process to improve oxide quality for non-volatile flash memory products Grant 6,306,707 - Foster , et al. October 23, 2	2001-10-23
Floating gate engineering to improve tunnel oxide reliability for flash memory devices Grant 6,153,470 - He , et al. November 28, 2	2000-11-28
Method of fabricating an oxynitride-capped high dielectric constant interpolysilicon dielectric structure for a low voltage non-volatile memory Grant 6,025,228 - Ibok , et al. February 15, 2	2000-02-15

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