Haycock; Matthew B.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Haycock; Matthew B..The latest application filed is for "integrated circuit passive signal distribution".

Company Profile

0.32.24

Haycock; Matthew B. - Beaverton OR US

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Integrated circuit passive signal distribution Grant 8,571,513 - O'Mahony , et al. October 29, 2	2013-10-29
Integrated Circuit Passive Signal Distribution App 20120281323 - O'Mahony; Frank ; et al.	2012-11-08
Integrated circuit passive signal distribution Grant 8,213,894 - O'Mahony , et al. July 3, 2	2012-07-03
Pulse amplitude modulated system with reduced intersymbol interference Grant 7,653,165 - Casper , et al. January 26, 2	2010-01-26
Pulse amplitude modulated system with reduced intersymbol interference App 20080181331 - Casper; Bryan K. ; et al.	2008-07-31
Pulse amplitude modulated system with reduced intersymbol interference Grant 7,391,834 - Casper , et al. June 24, 2	2008-06-24
Digital bus synchronizer for generating read reset signal Grant 7,328,361 - Haycock , et al. February 5, 2	2008-02-05
Integrated circuit passive signal distribution App 20070153445 - O'Mahony; Frank ; et al.	2007-07-05
Simultaneous bidirectional port with synchronization circuit to synchronize the port with another port Grant 7,222,208 - Haycock , et al. May 22, 2	2007-05-22
Simultaneous transmission and reception of signals in different frequency bands over a bus line Grant 7,177,288 - Mooney , et al. February 13, 2	2007-02-13
On-chip observability buffer to observer bus traffic Grant 7,171,510 - Haycock , et al. January 30, 2	2007-01-30
Method and unit for deskewing signals Grant 7,120,838 - Casper , et al. October 10, 2	2006-10-10
Systems for interchip communication App 20060110952 - Borkar; Shekhar Y. ; et al.	2006-05-25
Digital bus synchronizer for generating read reset signal App 20050248367 - Haycock, Matthew B. ; et al.	2005-11-10
Digital bus synchronizer for generating read reset signal Grant 6,901,526 - Haycock , et al. May 31, 2	2005-05-31
Low power NRZ interconnect for pulsed signaling Grant 6,894,536 - Martin , et al. May 17, 2	2005-05-17
Systems for interchip communication Grant 6,847,617 - Borkar , et al. January 25, 2	2005-01-25
Memory pass-band signaling Grant 6,845,424 - Casper , et al. January 18, 2	2005-01-18
Systems For Interchip Communication App 20040225778 - Borkar, Shekhar Y. ; et al.	2004-11-11
Bidirectional port with clock channel used for synchronization Grant 6,803,790 - Haycock , et al. October 12, 2	2004-10-12
Bidirectional port with clock channel used for synchronization Grant 6,791,356 - Haycock , et al. September 14, 2	2004-09-14
Integrated circuit stubs in a point-to-point system Grant 6,747,474 - Borkar , et al. June 8, 2	2004-06-08
Synchronous clock generator for integrated circuits Grant 6,741,107 - Borkar , et al. May 25, 2	2004-05-25
Bidirectional port with clock channel used for synchronization App 20040080338 - Haycock, Matthew B. ; et al.	2004-04-29
Method and apparatus for removing and installing a computer system bus agent without powering down the computer system Grant 6,718,416 - Self , et al. April 6, 2	2004-04-06
Pulse amplitude modulated system with reduced intersymbol interference App 20040062319 - Casper, Bryan K. ; et al.	2004-04-01
Voltage margin testing of a transmission line analog signal using a variable offset comparator in a data receiver circuit Grant 6,653,893 - Casper , et al. November 25, 2	2003-11-25
Apparatus for testing simultaneous bi-directional I/O circuits Grant 6,639,426 - Haycock , et al. October 28, 2	2003-10-28
Method and unit for deskewing signals App 20030188234 - Casper, Bryan K. ; et al.	2003-10-02
Memory pass-band signaling App 20030145162 - Casper, Bryan K. ; et al.	2003-07-31
Current mode bidirectional port with data channel used for synchronization Grant 6,597,198 - Haycock , et al. July 22, 2	2003-07-22
Low power NRZ interconnect for pulsed signaling App 20030107411 - Martin, Aaron K. ; et al.	2003-06-12
Simultaneous bi-directional channel separation App 20030101306 - Mooney, Stephen R. ; et al.	2003-05-29
Current Mode Bidirectional Port With Data Channel Used For Synchronization App 20030067325 - Haycock, Matthew B. ; et al.	2003-04-10
Method and apparatus for realigning bits on a parallel bus App 20030061527 - Haycock, Matthew B. ; et al.	2003-03-27
Transition reduction encoder using current and last bit sets Grant 6,538,584 - Borkar , et al. March 25, 2	2003-03-25
Receiver deskewing of multiple source synchronous bits from a parallel bus Grant 6,536,025 - Kennedy , et al. March 18, 2	2003-03-18
Voltage Mode Bidirectional Port With Data Channel Used For Synchronization App 20030048113 - Haycock, Matthew B. ; et al.	2003-03-13
Voltage mode bidirectional port with data channel used for synchronization Grant 6,529,037 - Haycock , et al. March 4, 2	2003-03-04
Bidirectional port with clock channel used for synchronization App 20030001618 - Haycock, Matthew B. ; et al.	2003-01-02
Voltage margin testing of a transmission line analog signal using a variable offset comparator in a data receiver circuit App 20030001667 - Casper, Bryan K. ; et al.	2003-01-02
Encoded bits over interconnects App 20020130794 - Borkar, Shekhar Y. ; et al.	2002-09-19
Synchronous clock generator for integrated circuits App 20020125925 - Borkar, Shekhar Y. ; et al.	2002-09-12
Integrated circuit stubs in a point-to-point system App 20020117745 - Borkar, Shekhar Y. ; et al.	2002-08-29
Biased control loop circuit for setting impedance of output driver Grant 6,424,175 - Vangal , et al. July 23, 2	2002-07-23
Observability buffer App 20020095622 - Haycock, Matthew B. ; et al.	2002-07-18
Rail-to-rail Input Clocked Amplifier App 20020084838 - Martin, Aaron K. ; et al.	2002-07-04
Using A Timing Strobe For Synchronization And Validation In A Digital Logic Device App 20020079928 - Borkar, Shekhar Y. ; et al.	2002-06-27
Apparatus and methods for testing simultaneous bi-directional I/O circuits App 20020079926 - Haycock, Matthew B. ; et al.	2002-06-27
Symmetric, voltage-controlled CMOS delay cell with closed-loop replica bias Grant 6,377,103 - Mooney , et al. April 23, 2	2002-04-23
Data and strobe repeater having a frequency control unit to re-time the data and reject delay variation in the strobe Grant 6,373,289 - Martin , et al. April 16, 2	2002-04-16
Apparatus and methods for testing simultaneous bi-directional I/O circuits Grant 6,348,811 - Haycock , et al. February 19, 2	2002-02-19
Digital variable-delay circuit having voltage-mixing interpolator and methods of testing input/output buffers using same Grant 6,348,826 - Mooney , et al. February 19, 2	2002-02-19
Impedance control circuit Grant 6,087,847 - Mooney , et al. July 11, 2	2000-07-11
3.3 V to 5 V supply interface buffer Grant 5,410,267 - Haycock , et al. April 25, 1	1995-04-25