Hayashi; Terumine

Patent Applications and Registrations

Patent applications and USPTO patent grants for Hayashi; Terumine.The latest application filed is for "method of determining routes for a plurality of wiring connections and a circuit board produced by such a method".

Company Profile

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Hayashi; Terumine - Hitachi JP

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Method of determining routes for a plurality of wiring connections and a circuit board produced by such a method Grant 5,657,242 - Sekiyama , et al. August 12, 1	1997-08-12
Placement optimizing method/apparatus and apparatus for designing semiconductor devices Grant 5,200,908 - Date , et al. April 6, 1	1993-04-06
Method and apparatus for optimizing element placement and method and apparatus for deciding the optimal element placement Grant 5,144,563 - Date , et al. September 1, 1	1992-09-01
Method for deleting unused gates and method for manufacturing master-slice semiconductor integrated circuit device using the deleting method Grant 4,960,724 - Watanabe , et al. October 2, 1	1990-10-02
Memory incorporating logic LSI and method for testing the same LSI Grant 4,956,818 - Hatayama , et al. September 11, 1	1990-09-11
Integrated circuit device Grant 4,701,922 - Kuboki , et al. October 20, 1	1987-10-20
Integrated circuit device and method of diagnosing the same Grant 4,613,970 - Masuda , et al. September 23, 1	1986-09-23

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