Havemann; Robert H.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Havemann; Robert H..The latest application filed is for "integrated circuit having a doped porous dielectric and method of manufacturing the same".

Company Profile

0.52.8

Havemann; Robert H. - San Jose CA
Havemann; Robert H. - Garland TX
Havemann; Robert H. - Pleasanton CA
Havemann; Robert H. - Plano TX

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Nanoparticle cap layer Grant 8,039,379 - Alers , et al. October 18, 2	2011-10-18
Nanoparticle cap layer Grant 7,994,640 - Alers , et al. August 9, 2	2011-08-09
Integrated circuit having a doped porous dielectric and method of manufacturing the same Grant 7,368,401 - Havemann May 6, 2	2008-05-06
Selective refractory metal and nitride capping Grant 7,157,798 - Fair , et al. January 2, 2	2007-01-02
Method of fabricating low dielectric constant dielectric films Grant 6,995,439 - Hill , et al. February 7, 2	2006-02-07
Inhomogeneous materials having physical properties decoupled from desired functions Grant 6,873,026 - Brunemeier , et al. March 29, 2	2005-03-29
Selective refractory metal and nitride capping Grant 6,844,258 - Fair , et al. January 18, 2	2005-01-18
Integrated circuit having a doped porous dielectric and method of manufacturing the same App 20040211991 - Havemann, Robert H.	2004-10-28
Method of fabricating low dielectric constant dielectric films Grant 6,753,250 - Hill , et al. June 22, 2	2004-06-22
Integrated circuit having a doped porous dielectric and method of manufacturing the same Grant 6,753,563 - Havemann June 22, 2	2004-06-22
Methods for forming a fuse in a semiconductor device Grant 6,677,188 - Havemann January 13, 2	2004-01-13
Methods For Forming A Fuse In A Semiconductor Device App 20040005776 - Havemann, Robert H.	2004-01-08
Zero overlap contact/via with metal plug App 20020086475 - Havemann, Robert H.	2002-07-04
Integrated circuit having a doped porous dielectric and method of manufacturing the same App 20020064969 - Havemann, Robert H.	2002-05-30
Low pressure, low temperature, semiconductor gap filling process App 20020064942 - Dixit, Girish A. ; et al.	2002-05-30
Surface modified interconnects App 20020038911 - Graas, Carole D. ; et al.	2002-04-04
Integrated circuit interconnect and method Grant 6,358,849 - Havemann , et al. March 19, 2	2002-03-19
Passivation of inlaid metallization Grant 6,355,559 - Havemann , et al. March 12, 2	2002-03-12
Enhancements To Polysilicon Gate App 20020000621 - HAVEMANN, ROBERT H.	2002-01-03
Transistor and method App 20010019872 - Havemann, Robert H.	2001-09-06
Integrated circuit insulator and structure using low dielectric insulator material including HSQ and fluorinated oxide Grant 6,278,174 - Havemann , et al. August 21, 2	2001-08-21
Transistor and method Grant 6,271,577 - Havemann August 7, 2	2001-08-07
Metallization method for porous dielectrics Grant 6,156,651 - Havemann December 5, 2	2000-12-05
Variable doping of metal plugs for enhanced reliability Grant 6,130,156 - Havemann , et al. October 10, 2	2000-10-10
Method to improve the texture of aluminum metallization Grant 6,077,782 - Hsu , et al. June 20, 2	2000-06-20
Multilevel interconnect structure with air gaps formed between metal leads Grant 5,936,295 - Havemann , et al. August 10, 1	1999-08-10
Process for conductors with selective deposition Grant 5,891,804 - Havemann , et al. April 6, 1	1999-04-06
Interconnect capacitance between metal leads Grant 5,814,558 - Jeng , et al. September 29, 1	1998-09-29
Method of dual masking for selective gap fill of submicron interconnects Grant 5,789,319 - Havemann , et al. August 4, 1	1998-08-04
Structure with selective gap fill of submicron interconnects Grant 5,789,818 - Havemann August 4, 1	1998-08-04
Interconnect structure with an integrated low density dielectric Grant 5,747,880 - Havemann , et al. May 5, 1	1998-05-05
Two-step metal etch process for selective gap fill of submicron inter-connects and structure for same Grant 5,728,628 - Havemann March 17, 1	1998-03-17
Multilevel interconnect structure with air gaps formed between metal leads Grant 5,668,398 - Havemann , et al. September 16, 1	1997-09-16
Diffusion barrier trilayer for minimizing reaction between metallization layers of integrated circuits Grant 5,668,411 - Hong , et al. September 16, 1	1997-09-16
Porous dielectric material with a passivation layer for electronics applications Grant 5,661,344 - Havemann , et al. August 26, 1	1997-08-26
Method of making an interconnect structure with an integrated low density dielectric Grant 5,488,015 - Havemann , et al. January 30, 1	1996-01-30
Method of fabricating a self-aligned contact using organic dielectric materials Grant 5,482,894 - Havemann January 9, 1	1996-01-09
Method of fabricating porous dielectric material with a passivation layer for electronics applications Grant 5,472,913 - Havemann , et al. December 5, 1	1995-12-05
Method of making thin film transistor and a silicide local interconnect Grant 5,468,662 - Havemann November 21, 1	1995-11-21
Polysilicon resistor structure including polysilicon contacts Grant 5,465,005 - Eklund , et al. November 7, 1	1995-11-07
Multilevel interconnect structure with air gaps formed between metal leads Grant 5,461,003 - Havemann , et al. October 24, 1	1995-10-24
Method of making thin film transistor and a silicide local interconnect Grant 5,403,759 - Havemann April 4, 1	1995-04-04
Refractory metal silicide deposition process Grant 5,395,798 - Havemann March 7, 1	1995-03-07
Process for reduced emitter-base capacitance in bipolar transistor Grant 5,374,845 - Havemann December 20, 1	1994-12-20
Process for obtaining high barrier Schottky diode and local interconnect Grant 5,320,971 - Eklund , et al. June 14, 1	1994-06-14
Method of making MOS VLSI semiconductor device with metal gate Grant 5,252,502 - Havemann October 12, 1	1993-10-12
Method for forming shallow junctions with a low resistivity silicide layer Grant 5,217,924 - Rodder , et al. June 8, 1	1993-06-08
Process for fabricating a BiCMOS integrated circuit Grant 5,124,271 - Havemann June 23, 1	1992-06-23
Process for reduced emitter-base capacitance in bipolar transistor Grant 5,013,671 - Havemann May 7, 1	1991-05-07
Bipolar transistor with a sidewall-diffused subcollector Grant 5,003,365 - Havemann , et al. March 26, 1	1991-03-26
Method for forming a transistor base region under thick oxide Grant 4,958,213 - Eklund , et al. September 18, 1	1990-09-18
Bipolar process for forming shallow NPN emitters Grant 4,877,748 - Havemann October 31, 1	1989-10-31
Bicmos process for forming shallow npn emitters and mosfet source/drains Grant 4,816,423 - Havemann March 28, 1	1989-03-28
Process for formation of shallow silicided junctions Grant 4,788,160 - Havemann , et al. November 29, 1	1988-11-29
Method for forming self-aligned emitters and bases and source/drains in an integrated circuit Grant 4,774,204 - Havemann September 27, 1	1988-09-27
Method of making vertical bipolar transistor having base above buried nitride dielectric formed by deep implantation Grant 4,706,378 - Havemann November 17, 1	1987-11-17
Technique for fabricating a sidewall base contact with extrinsic base-on-insulator Grant 4,703,554 - Havemann November 3, 1	1987-11-03
Laser-enhanced drive in of source and drain diffusions Grant 4,621,411 - Havemann , et al. November 11, 1	1986-11-11
Semiconductor processing facility for providing enhanced oxidation rate Grant 4,599,247 - Bean , et al. July 8, 1	1986-07-08
Trench isolation process for integrated circuit devices Grant 4,597,164 - Havemann July 1, 1	1986-07-01