Hauviller; Philippe

Patent Applications and Registrations

Patent applications and USPTO patent grants for Hauviller; Philippe.The latest application filed is for "method of checking the layout integrity".

Company Profile

0.8.12

Hauviller; Philippe - Itteville FR
Hauviller; Philippe - Evry FR

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Method Of Checking The Layout Integrity App 20150347667 - Ellis-Monaghan; John J. ; et al.	2015-12-03
Characterizing jitter sensitivity of a serializer/deserializer circuit Grant 7,543,209 - Bonneau , et al. June 2, 2	2009-06-02
Serializer/deserializer circuit for jitter sensitivity characterization Grant 7,533,317 - Bonneau , et al. May 12, 2	2009-05-12
Very High Speed Low Power Receiver Equalization System For Non-Return-To-Zero Transmission App 20080279271 - Hauviller; Philippe ; et al.	2008-11-13
Esd Power Clamp In Triple Well App 20080029824 - Baizley; Arnold E. ; et al.	2008-02-07
Serializer/deserializer Circuit For Jitter Sensitivity Characterization App 20070277069 - Bonneau; Dominique P. ; et al.	2007-11-29
Serializer/deserializer circuit for jitter sensitivity characterization Grant 7,251,764 - Bonneau , et al. July 31, 2	2007-07-31
Serializer/deserializer circuit for jitter sensitivity characterization App 20070088998 - Bonneau; Dominique P. ; et al.	2007-04-19
Receiver having full signal path differential offset cancellation capabilities Grant 7,180,354 - Gabillard , et al. February 20, 2	2007-02-20
Transition detection, validation and memorization circuit Grant 7,180,966 - Vallet , et al. February 20, 2	2007-02-20
Sample selection and data alignment circuit Grant 7,136,443 - Vallet , et al. November 14, 2	2006-11-14
An Improved Receiver Having Full Signal Path Differential Offset Cancellation Capabilities App 20050212564 - Gabillard, Bertrand ; et al.	2005-09-29
Differential sampling circuit for generating a differential input signal DC offset Grant 6,946,986 - Gabillard , et al. September 20, 2	2005-09-20
Improvements To Data Recovery Circuits Using Oversampling For Isi Compensation App 20050135518 - Vallet, Vincent ; et al.	2005-06-23
Built-in self test system and method for high speed clock and data recovery circuit Grant 6,834,367 - Bonneau , et al. December 21, 2	2004-12-21
Serializer/deserializer Circuit For Jitter Sensitivity Characterization App 20040243899 - Bonneau, Dominique P. ; et al.	2004-12-02
Differential sampling circuit for generating a differential input signal DC offset App 20040130468 - Gabillard, Bertrand ; et al.	2004-07-08
Sample selection and data alignment circuit App 20030095619 - Vallet, Vincent ; et al.	2003-05-22
Transition detection, validation and memorization circuit App 20030091137 - Vallet, Vincent ; et al.	2003-05-15
Built-in self test system and method for high speed clock and data recovery circuit App 20010016929 - Bonneau, Dominique P. ; et al.	2001-08-23

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