Hause; Fred

Patent Applications and Registrations

Patent applications and USPTO patent grants for Hause; Fred.The latest application filed is for "heat dissipation in temperature critical device areas of semiconductor devices by heat pipes connecting to the substrate backside".

Company Profile

0.22.6

Hause; Fred - Austin TX US

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Electronic device and method of biasing Grant 8,687,417 - Li , et al. April 1, 2	2014-04-01
Heat dissipation in temperature critical device areas of semiconductor devices by heat pipes connecting to the substrate backside Grant 8,564,120 - Mowry , et al. October 22, 2	2013-10-22
Thyristor semiconductor device and method of manufacture Grant 7,804,107 - Horch , et al. September 28, 2	2010-09-28
Heat Dissipation In Temperature Critical Device Areas Of Semiconductor Devices By Heat Pipes Connecting To The Substrate Backside App 20100164093 - Mowry; Anthony ; et al.	2010-07-01
Method of optimizing sidewall spacer size for silicide proximity with in-situ clean Grant 7,745,337 - Farber , et al. June 29, 2	2010-06-29
Air gap spacer formation Grant 7,741,663 - Hause , et al. June 22, 2	2010-06-22
Air Gap Spacer Formation App 20100102363 - Hause; Fred ; et al.	2010-04-29
MOS structures with contact projections for lower contact resistance and methods for fabricating the same Grant 7,670,932 - Zhu , et al. March 2, 2	2010-03-02
Method Of Optimizing Sidewall Spacer Size For Silicide Proximity With In-situ Clean App 20090286389 - Farber; David G. ; et al.	2009-11-19
Electronic Device And Method Of Biasing App 20090090969 - Li; Ruigang ; et al.	2009-04-09
Mos Structures With Contact Projections For Lower Contact Resistance And Methods For Fabricating The Same App 20080308879 - ZHU; Jianhong ; et al.	2008-12-18
Method of manufacturing a thyristor semiconductor device Grant 7,279,367 - Horch , et al. October 9, 2	2007-10-09
Method of manufacturing semiconductor device having nickel silicide with reduced interface roughness Grant 6,967,160 - Paton , et al. November 22, 2	2005-11-22
Method of forming local interconnect barrier layers App 20050101120 - Hause, Fred ; et al.	2005-05-12
Thyrister semiconductor device Grant 6,888,176 - Horch , et al. May 3, 2	2005-05-03
Nickel silicide with reduced interface roughness Grant 6,873,051 - Paton , et al. March 29, 2	2005-03-29
Semiconductor device having metal gate electrode and titanium or tantalum nitride gate dielectric barrier layer and process of fabrication thereof Grant 6,225,168 - Gardner , et al. May 1, 2	2001-05-01
Metal attachment method and structure for attaching substrates at low temperatures Grant 6,097,096 - Gardner , et al. August 1, 2	2000-08-01
Metal attachment method and structure for attaching substrates at low temperatures Grant 6,080,640 - Gardner , et al. June 27, 2	2000-06-27
Elevated local interconnect and contact structure Grant 6,054,385 - Gardner , et al. April 25, 2	2000-04-25
Semiconductor substrate having extended scribe line test structure and method of fabrication thereof Grant 6,027,859 - Dawson , et al. February 22, 2	2000-02-22
High performance MOSFET structure having asymmetrical spacer formation and having source and drain regions with different doping concentration Grant 5,952,702 - Gardner , et al. September 14, 1	1999-09-14
High performance asymmetrical MOSFET structure and method of making the same Grant 5,841,168 - Gardner , et al. November 24, 1	1998-11-24
Method of forming a multiple transistor channel doping using a dual resist fabrication sequence Grant 5,827,763 - Gardner , et al. October 27, 1	1998-10-27
Method of fabricating FET or CMOS transistors using MeV implantation Grant 5,821,146 - Chang , et al. October 13, 1	1998-10-13
High performance mosfet structure having asymmetrical spacer formation and method of making the same Grant 5,789,298 - Gardner , et al. August 4, 1	1998-08-04

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