Hatti; Sunil Suresh

Patent Applications and Registrations

Patent applications and USPTO patent grants for Hatti; Sunil Suresh.The latest application filed is for "light weight and high throughput test case generation methodology for testing cache/tlb intervention and diagnostics".

Company Profile

0.15.17

Hatti; Sunil Suresh - Gokul IN
Hatti; Sunil Suresh - Karnataka IN
Hatti; Sunil Suresh - Bangalore IN

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Predicting lwarx and stwcx instructions in test pattern generation and simulation for processor design verification/validation in interrupt mode Grant 8,127,192 - Arora , et al. February 28, 2	2012-02-28
System and method for generating fast instruction and data interrupts for processor design verification and validation Grant 8,099,559 - Choudhury , et al. January 17, 2	2012-01-17
System and method for efficiently testing cache congruence classes during processor design verification and validation Grant 8,019,566 - Bussa , et al. September 13, 2	2011-09-13
System and method for testing multiple processor modes for processor design verification and validation Grant 8,006,221 - Arora , et al. August 23, 2	2011-08-23
System and method for testing a large memory area during processor design verification and validation Grant 7,992,059 - Anvekar , et al. August 2, 2	2011-08-02
Light weight and high throughput test case generation methodology for testing cache/TLB intervention and diagnostics Grant 7,966,521 - Bussa , et al. June 21, 2	2011-06-21
System and method for testing SLB and TLB cells during processor design verification and validation Grant 7,797,650 - Bag , et al. September 14, 2	2010-09-14
System and method for using resource pools and instruction pools for processor design verification and validation Grant 7,752,499 - Choudhury , et al. July 6, 2	2010-07-06
System and method for creating different start cache and bus states using multiple test patterns for processor design verification and validation Grant 7,747,908 - Choudhury , et al. June 29, 2	2010-06-29
System and method for increasing error checking performance by calculating CRC calculations after multiple test patterns for processor design verification and validation Grant 7,739,570 - Bag , et al. June 15, 2	2010-06-15
System and method for predicting lwarx and stwcx instructions in test pattern generation and simulation for processor design verification and validation Grant 7,689,886 - Arora , et al. March 30, 2	2010-03-30
System and method for re-shuffling test case instruction orders for processor design verification and validation Grant 7,669,083 - Arora , et al. February 23, 2	2010-02-23
System and method for verification of cache snoop logic and coherency between instruction & data caches for processor design verification and validation Grant 7,661,023 - Arora , et al. February 9, 2	2010-02-09
Light Weight And High Throughput Test Case Generation Methodology For Testing Cache/tlb Intervention And Diagnostics App 20100011248 - Bussa; Vinod ; et al.	2010-01-14
System and method of testing using test pattern re-execution in varying timing scenarios for processor design verification and validation Grant 7,647,539 - Bussa , et al. January 12, 2	2010-01-12
Generating a Test Case Micro Generator During Processor Design Verification and Validation App 20090307468 - Choudhury; Shubhodeep Roy ; et al.	2009-12-10
System and method for pseudo-random test pattern memory allocation for processor design verification and validation Grant 7,584,394 - Choudhury , et al. September 1, 2	2009-09-01
System and Method for Efficiently Handling Interrupts App 20090070570 - Choudhury; Shubhodeep Roy ; et al.	2009-03-12
System and Method for Re-Shuffling Test Case Instruction Orders for Processor Design Verification and Validation App 20090070631 - Arora; Sampan ; et al.	2009-03-12
System and Method for Efficiently Testing Cache Congruence Classes During Processor Design Verification and Validation App 20090070532 - Bussa; Vinod ; et al.	2009-03-12
System and Method for Using Resource Pools and Instruction Pools for Processor Design Verification and Validation App 20090070768 - Choudhury; Shubhodeep Roy ; et al.	2009-03-12
System and Method for Testing SLB and TLB Cells During Processor Design Verification and Validation App 20090070632 - Bag; Sandip ; et al.	2009-03-12
System and Method for Generating Fast Instruction and Data Interrupts for Processor Design Verification and Validation App 20090070546 - Choudhury; Shubhodeep Roy ; et al.	2009-03-12
System and Method for Testing a Large Memory Area During Processor Design Verification and Validation App 20090070643 - Anvekar; Divya Subbarao ; et al.	2009-03-12
System and Method for Testing Multiple Processor Modes for Processor Design Verification and Validation App 20090070629 - Arora; Sampan ; et al.	2009-03-12
System And Method For Predicting Iwarx And Stwcx Instructions In Test Pattern Generation And Simulation For Processor Design Verification/validation In Interrupt Mode App 20090024894 - Arora; Sampan ; et al.	2009-01-22
System and Method for Verification of Cache Snoop Logic and Coherency Between Instruction & Data Caches for Processor Design Verification and Validation App 20090024876 - Arora; Sampan ; et al.	2009-01-22
System and Method for Pseudo-Random Test Pattern Memory Allocation for Processor Design Verification and Validation App 20090024891 - Choudhury; Shubhodeep Roy ; et al.	2009-01-22
System and Method of Testing using Test Pattern Re-Execution in Varying Timing Scenarios for Processor Design Verification and Validation App 20090024892 - Bussa; Vinod ; et al.	2009-01-22
System and Method for Predicting lwarx and stwcx Instructions in Test Pattern Generation and Simulation for Processor Design Verification and Validation App 20090024886 - Arora; Sampan ; et al.	2009-01-22
System and Method for Increasing Error Checking Performance by Calculating CRC Calculations After Multiple Test Patterns for Processor Design Verification and Validation App 20090024873 - Bag; Sandip ; et al.	2009-01-22
System and Method for Creating Different Start Cache and Bus States Using Multiple Test Patterns for Processor Design Verification and Validation App 20090024877 - Choudhury; Shubhodeep Roy ; et al.	2009-01-22

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