Hathaway; David James

Patent Applications and Registrations

Patent applications and USPTO patent grants for Hathaway; David James.The latest application filed is for "method for reticle shapes analysis and correction".

Company Profile

0.11.4

Hathaway; David James - Underhill VT
Hathaway; David James - Underhill Center VT
Hathaway; David James - Chittenden County VT
Hathaway; David James - Underhill Ctr. VT

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Compensation of process and voltage variability in multi-threshold dynamic voltage scaling circuits Grant 7,525,373 - Ogilvie , et al. April 28, 2	2009-04-28
Method and system for performing shapes correction of a multi-cell reticle photomask design Grant 7,302,673 - Habitz , et al. November 27, 2	2007-11-27
Method For Reticle Shapes Analysis And Correction App 20070061771 - Habitz; Peter Anton ; et al.	2007-03-15
Method and apparatus for efficient utilization of electronic fuse source connections Grant 7,082,065 - Hathaway , et al. July 25, 2	2006-07-25
Method And Apparatus For Efficient Utilization Of Electronic Fuse Source Connections App 20060091904 - Hathaway; David James ; et al.	2006-05-04
Method and system for fault-tolerant static timing analysis Grant 6,795,951 - Hathaway , et al. September 21, 2	2004-09-21
Stacked voltage rails for low-voltage DC distribution Grant 6,479,974 - Cohn , et al. November 12, 2	2002-11-12
Method and system for fault-tolerant static timing analysis App 20020112195 - Hathaway, David James ; et al.	2002-08-15
Stacked voltage rails for low-voltage DC distribution App 20020084824 - Cohn, John Maxwell ; et al.	2002-07-04
Double-edge-triggered flip-flop providing two data transitions per clock cycle Grant 6,300,809 - Gregor , et al. October 9, 2	2001-10-09
Method to partition clock sinks into nets Grant 5,963,728 - Hathaway , et al. October 5, 1	1999-10-05
Adaptive incremental placement of circuits on VLSI chip Grant 5,757,657 - Hathaway , et al. May 26, 1	1998-05-26
Localized simulated annealing Grant 5,745,735 - Cohn , et al. April 28, 1	1998-04-28
Method for clock skew cost calculation Grant 5,740,067 - Hathaway April 14, 1	1998-04-14
Wiring design tool improvement for avoiding electromigration by determining optimal wire widths Grant 5,737,580 - Hathaway , et al. April 7, 1	1998-04-07

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.