HARTSWICK; Thomas J.

Patent Applications and Registrations

Patent applications and USPTO patent grants for HARTSWICK; Thomas J..The latest application filed is for "semiconductor structures having low resistance paths throughout a wafer".

Company Profile

3.10.9

HARTSWICK; Thomas J. - Underhill VT

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Semiconductor Structures Having Low Resistance Paths Throughout A Wafer App 20190362977 - GAMBINO; Jeffrey P. ; et al.	2019-11-28
Semiconductor structures having low resistance paths throughout a wafer Grant 10,438,803 - Gambino , et al. O	2019-10-08
Semiconductor structures having low resistance paths throughout a wafer Grant 10,177,000 - Gambino , et al. J	2019-01-08
Wafer with plated wires and method of fabricating same Grant 10,134,670 - Hartswick , et al. November 20, 2	2018-11-20
Semiconductor structures having low resistance paths throughout a wafer Grant 9,691,623 - Gambino , et al. June 27, 2	2017-06-27
Semiconductor Structures Having Low Resistance Paths Throughout A Wafer App 20170148672 - GAMBINO; Jeffrey P. ; et al.	2017-05-25
Semiconductor structures having low resistance paths throughout a wafer Grant 9,620,371 - Gambino , et al. April 11, 2	2017-04-11
Semiconductor structures having low resistance paths throughout a wafer Grant 9,478,427 - Gambino , et al. October 25, 2	2016-10-25
Wafer With Plated Wires And Method Of Fabricating Same App 20160300793 - Hartswick; Thomas J. ; et al.	2016-10-13
Semiconductor Structures Having Low Resistance Paths Throughout A Wafer App 20160284645 - GAMBINO; Jeffrey P. ; et al.	2016-09-29
Semiconductor structures having low resistance paths throughout a wafer Grant 9,312,140 - Gambino , et al. April 12, 2	2016-04-12
Semiconductor Structures Having Low Resistance Paths Throughout A Wafer App 20150364416 - GAMBINO; Jeffrey P. ; et al.	2015-12-17
Semiconductor Structures Having Low Resistance Paths Throughout A Wafer App 20150364368 - GAMBINO; Jeffrey P. ; et al.	2015-12-17
Semiconductor Structures Having Low Resistance Paths Throughout A Wafer App 20150364367 - GAMBINO; Jeffrey P. ; et al.	2015-12-17
Semiconductor Structures Having Low Resistance Paths Throughout A Wafer App 20150332925 - GAMBINO; Jeffrey P. ; et al.	2015-11-19
Method of designing and structure for visual and electrical test of semiconductor devices Grant 6,627,926 - Hartswick , et al. September 30, 2	2003-09-30
Method of designing and structure for visual and electrical test of semiconductor devices App 20010005052 - Hartswick, Thomas J. ; et al.	2001-06-28
Interconnects using metal spacers and method for forming same Grant 5,926,738 - Cronin , et al. July 20, 1	1999-07-20
Process for forming refractory metal silicide layers of different thicknesses in an integrated circuit Grant 5,034,348 - Hartswick , et al. July 23, 1	1991-07-23

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