Hartner; Tobias
Patent Applications and Registrations
Patent applications and USPTO patent grants for Hartner; Tobias.The latest application filed is for "memory chip having an integrated address scrambler unit and method for scrambling an address in an integrated memory".
- Hartner; Tobias - Hamburg DE
- Hartner; Tobias - Munich DE
- Hartner, Tobias - Munchen DE
| Patent | Date |
|---|---|
| Integrated semiconductor circuit having a cell array having a multiplicity of memory cells Grant 6,998,664 - Vollrath , et al. February 14, 2 | 2006-02-14 |
| Integrated semiconductor circuit having a multiplicity of memory cells Grant 6,967,370 - Schroder , et al. November 22, 2 | 2005-11-22 |
| Memory chip having an integrated address scrambler unit and method for scrambling an address in an integrated memory App 20040260934 - Proll, Manfred ; et al. | 2004-12-23 |
| On chip scrambling Grant 6,826,111 - Schneider , et al. November 30, 2 | 2004-11-30 |
| Integrated semiconductor circuit having a multiplicity of memory cells App 20040201051 - Schroder, Stephan ; et al. | 2004-10-14 |
| Integrated semiconductor circuit having a cell array having a multiplicity of memory cells App 20040196711 - Vollrath, Joerg ; et al. | 2004-10-07 |
| On chip scrambling App 20030048672 - Schneider, Ralf ; et al. | 2003-03-13 |
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