| Patent | Date |
|---|
Epipolar reconstruction of 3D structures
Grant 5,559,334 - Gupta , et al. September 24, 1 | 1996-09-24 |
Method of calibration of imaging devices
Grant 5,550,376 - Gupta , et al. August 27, 1 | 1996-08-27 |
Classifying and sorting crystalline objects
Grant 5,544,254 - Hartley , et al. August 6, 1 | 1996-08-06 |
Method of achieving reduced dose X-ray fluoroscopy by employing statistical estimation of poisson noise
Grant 5,396,531 - Hartley March 7, 1 | 1995-03-07 |
Correlation methods of identifying defects in imaging devices
Grant 5,361,307 - Hartley , et al. November 1, 1 | 1994-11-01 |
Unitary transform methods of identifying defects in imaging devices
Grant 5,325,198 - Hartley , et al. June 28, 1 | 1994-06-28 |
Systolic array processors for reducing under-utilization of original design parallel-bit processors with digit-serial processors by using maximum common divisor of latency around the loop connection
Grant 5,317,755 - Hartley , et al. May 31, 1 | 1994-05-31 |
X-ray fluoroscopy system for reducing dosage employing iterative power ratio estimation
Grant 5,293,415 - Hartley , et al. March 8, 1 | 1994-03-08 |
Array multiplier adapted for tiled layout by silicon compiler
Grant 5,291,431 - Ho , et al. March 1, 1 | 1994-03-01 |
Forming, with the aid of an overview image, a composite image from a mosaic of images
Grant 5,187,754 - Currin , et al. February 16, 1 | 1993-02-16 |
Measuring velocity of a target by Doppler shift, using improvements in calculating discrete Fourier transform
Grant 5,177,691 - Welles , et al. January 5, 1 | 1993-01-05 |
Computer-aided design method for restructuring computational networks to minimize shimming delays
Grant 5,175,843 - Casavant , et al. December 29, 1 | 1992-12-29 |
Data format converters for use with digit-serial signals
Grant 5,164,724 - Hartley , et al. November 17, 1 | 1992-11-17 |
Buffer integrated circuit providing testing interface
Grant 5,159,598 - Welles, II , et al. October 27, 1 | 1992-10-27 |
Testing of integrated circuits including internal test circuitry and using token passing to select testing ports
Grant 5,119,378 - Welles, II , et al. June 2, 1 | 1992-06-02 |
Digit-serial linear combining apparatus
Grant 5,084,834 - Hartley , et al. January 28, 1 | 1992-01-28 |
Increased performance of digital integrated circuits by processing with multiple-bit-width digits
Grant 5,025,257 - Hartley , et al. June 18, 1 | 1991-06-18 |
Digit-serial linear combining apparatus useful in dividers
Grant 5,010,511 - Hartley , et al. April 23, 1 | 1991-04-23 |
Computation of discrete fourier transform using recursive techniques
Grant 4,972,358 - Welles II , et al. November 20, 1 | 1990-11-20 |
Cell stack for variable digit width serial architecture
Grant 4,951,221 - Corbett , et al. August 21, 1 | 1990-08-21 |
To-digit-serial converters for systems processing data in digit-serial format
Grant 4,942,396 - Hartley , et al. July 17, 1 | 1990-07-17 |
Low-latency two's complement bit-serial multiplier
Grant 4,860,240 - Hartley , et al. August 22, 1 | 1989-08-22 |
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