Hartig; Carsten

Patent Applications and Registrations

Patent applications and USPTO patent grants for Hartig; Carsten.The latest application filed is for "method for in-die overlay control using feol dummy fill layer".

Company Profile

0.15.17

Hartig; Carsten - Meerane DE

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Method for in-die overlay control using FEOL dummy fill layer Grant 10,115,621 - Moll , et al. October 30, 2	2018-10-30
Method For In-die Overlay Control Using Feol Dummy Fill Layer App 20170330782 - MOLL; Peter ; et al.	2017-11-16
Systems and methods for fabricating semiconductor device structures Grant 9,177,873 - Vaid , et al. November 3, 2	2015-11-03
Inline residual layer detection and characterization post via post etch using CD-SEM Grant 9,171,765 - Fischer , et al. October 27, 2	2015-10-27
Inline Residual Layer Detection And Characterization Post Via Post Etch Using Cd-sem App 20150243568 - FISCHER; Daniel ; et al.	2015-08-27
Layout For Reticle And Wafer Scanning Electron Microscope Registration Or Overlay Measurements App 20150221565 - NING; Guo Xiang ; et al.	2015-08-06
Detection of particle contamination on wafers Grant 9,091,667 - Urbanowicz , et al. July 28, 2	2015-07-28
Layout for reticle and wafer scanning electron microscope registration or overlay measurements Grant 9,029,855 - Ning , et al. May 12, 2	2015-05-12
Detection Of Particle Contamination On Wafers App 20150115153 - Urbanowicz; Adam Michal ; et al.	2015-04-30
Systems And Methods For Fabricating Semiconductor Device Structures App 20150033201 - Vaid; Alok ; et al.	2015-01-29
Systems and methods for fabricating semiconductor device structures using different metrology tools Grant 8,892,237 - Vaid , et al. November 18, 2	2014-11-18
Layout For Reticle And Wafer Scanning Electron Microscope Registration Or Overlay Measurements App 20140264334 - NING; Guo Xiang ; et al.	2014-09-18
Systems And Methods For Fabricating Semiconductor Device Structures Using Different Metrology Tools App 20140273299 - Vaid; Alok ; et al.	2014-09-18
Incorporating film optical property measurements into scatterometry metrology Grant 7,663,766 - Hartig , et al. February 16, 2	2010-02-16
Incorporating Film Optical Property Measurements Into Scatterometry Metrology App 20090059240 - Hartig; Carsten ; et al.	2009-03-05
Method of reducing contamination by removing an interlayer dielectric from the substrate edge Grant 7,410,885 - Schuehrer , et al. August 12, 2	2008-08-12
Technique for forming a passivation layer prior to depositing a barrier layer in a copper metallization layer Grant 7,259,091 - Schuehrer , et al. August 21, 2	2007-08-21
Method Of Reducing Contamination By Removing An Interlayer Dielectric From The Substrate Edge App 20070026670 - Schuehrer; Holger ; et al.	2007-02-01
Method of compensating for etch rate non-uniformities by ion implantation Grant 7,098,140 - Schaller , et al. August 29, 2	2006-08-29
Technique for forming a passivation layer prior to depositing a barrier layer in a copper metallization layer App 20060024951 - Schuehrer; Holger ; et al.	2006-02-02
Method of defining the dimensions of circuit elements by using spacer deposition techniques Grant 6,936,383 - Mazur , et al. August 30, 2	2005-08-30
System and method for wafer-based controlled patterning of features with critical dimensions Grant 6,838,010 - Grasshoff , et al. January 4, 2	2005-01-04
Method of compensating for etch rate non-uniformities by ion implantation App 20040266200 - Schaller, Matthias ; et al.	2004-12-30
Method and an apparatus for determining the dimension of a feature by varying a resolution determining parameter App 20040084619 - Hartig, Carsten ; et al.	2004-05-06
Die corner alignment structure Grant 6,724,096 - Werner , et al. April 20, 2	2004-04-20
Method of forming a substrate contact in a field effect transistor formed over a buried insulator layer Grant 6,720,242 - Burbach , et al. April 13, 2	2004-04-13
Method of defining the dimensions of circuit elements by using spacer deposition techniques App 20040002217 - Mazur, Martin ; et al.	2004-01-01
System and method for wafer-based controlled patterning of features with critical dimensions App 20030015493 - Grasshoff, Gunter ; et al.	2003-01-23
Die corner alignment structure App 20020185753 - Werner, Thomas ; et al.	2002-12-12
Method of forming a substrate contact in a field effect transistor formed over a buried insulator layer App 20020055244 - Burbach, Gert ; et al.	2002-05-09

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