Hartano; Ismed D. S.
Patent Applications and Registrations
Patent applications and USPTO patent grants for Hartano; Ismed D. S..The latest application filed is for "technique for debugging an integrated circuit having a parallel scan-chain architecture".
- Hartano; Ismed D. S. - Castro Valley CA
| Patent | Date |
|---|---|
| Technique for debugging an integrated circuit having a parallel scan-chain architecture Grant 6,941,498 - Hartano , et al. September 6, 2 | 2005-09-06 |
| Technique for debugging an integrated circuit having a parallel scan-chain architecture App 20030172334 - Hartano, Ismed D.S. ; et al. | 2003-09-11 |
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