Harper; Peter R.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Harper; Peter R..The latest application filed is for "wafer level optical module".

Company Profile

4.27.33

Harper; Peter R. - Gilroy CA
Harper; Peter R. - Morgan Hill CA
Harper; Peter R. - Lucas TX US
Harper; Peter R. - Round Rock TX

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Wafer level optical module Grant 10,993,317 - He , et al. April 27, 2	2021-04-27
Wafer level optical module Grant 10,811,400 - He , et al. October 20, 2	2020-10-20
Wafer Level Optical Module App 20200107435 - He; Yinjuan ; et al.	2020-04-02
Wafer Level Optical Module App 20200107436 - He; Yinjuan ; et al.	2020-04-02
Enhanced board level reliability for wafer level packages Grant 9,837,368 - Harper , et al. December 5, 2	2017-12-05
Wafer level device and method with cantilever pillar structure Grant 9,806,047 - Thambidurai , et al. October 31, 2	2017-10-31
Semiconductor package device having passive energy components Grant 9,564,415 - Harper February 7, 2	2017-02-07
Wafer-level passive device integration Grant 9,324,687 - Kelkar , et al. April 26, 2	2016-04-26
Multichip wafer level package (WLP) optical device Grant 9,322,901 - Kerness , et al. April 26, 2	2016-04-26
Multi-die, high current wafer level package Grant 9,230,903 - Samoilov , et al. January 5, 2	2016-01-05
Multi-die, High Current Wafer Level Package App 20150325512 - Samoilov; Arkadii V. ; et al.	2015-11-12
Wafer Level Device And Method With Cantilever Pillar Structure App 20150279799 - Thambidurai; Karthik ; et al.	2015-10-01
Enhanced Board Level Reliability For Wafer Level Packages App 20150255413 - Harper; Peter R. ; et al.	2015-09-10
Multi-die, high current wafer level package Grant 9,087,779 - Samoilov , et al. July 21, 2	2015-07-21
Semiconductor device having a buffer material and stiffener Grant 8,878,350 - Sridharan , et al. November 4, 2	2014-11-04
Semiconductor Device Having A Buffer Material And Stiffener App 20140306337 - Sridharan; Vivek S. ; et al.	2014-10-16
Method of forming an integrated circuit package including a direct connect pad, a blind via, and a bond pad electrically coupled to the direct connect pad Grant 8,828,799 - Rhyner , et al. September 9, 2	2014-09-09
Multichip Wafer Level Package (wlp) Optical Device App 20140231635 - Kerness; Nicole D. ; et al.	2014-08-21
Multi-die, High Current Wafer Level Package App 20140183747 - Samoilov; Arkadii V. ; et al.	2014-07-03
Semiconductor Package Device Having Passive Energy Components App 20140077385 - Harper; Peter R.	2014-03-20
Three-dimensional Semiconductor Package Device Having Enhanced Security App 20140077355 - Harper; Peter R. ; et al.	2014-03-20
Integrated circuit package including a direct connect pad, a blind via, and a bond pad electrically coupled to the direct connect pad Grant 8,598,048 - Rhyner , et al. December 3, 2	2013-12-03
Method of Forming an Integrated Circuit Package Including a Direct Connect Pad, A Blind Via, and a Bond Pad Electrically Coupled to the Direct Connect Pad App 20130295722 - Rhyner; Kenneth Robert ; et al.	2013-11-07
Integrated circuit stacked package precursors and stacked packaged devices and systems therefrom Grant 8,377,746 - Harper , et al. February 19, 2	2013-02-19
Integrated Circuit Package Including A Direct Connect Pad, A Blind Via, And A Bond Pad Electrically Coupled To The Direct Connect Pad App 20130026642 - Rhyner; Kenneth Robert ; et al.	2013-01-31
Integrated Circuit Stacked Package Precursors and Stacked Packaged Devices and Systems Therefrom App 20120015478 - Harper; Peter R. ; et al.	2012-01-19
Bga Package With Traces For Plating Pads Under The Chip App 20120013003 - RHYNER; KENNETH R. ; et al.	2012-01-19
BGA package with traces for plating pads under the chip Grant 8,053,349 - Rhyner , et al. November 8, 2	2011-11-08
Integrated circuit stacked package precursors and stacked packaged devices and systems therefrom Grant 8,049,320 - Harper , et al. November 1, 2	2011-11-01
Semiconductor device having wafer level chip scale packaging substrate decoupling Grant 7,919,860 - Murugan , et al. April 5, 2	2011-04-05
Integrated Circuit Package With Emi Shield App 20100006987 - Murugan; Rajen ; et al.	2010-01-14
Packaged Integrated Circuit Having Conformal Electromagnetic Shields And Methods To Form The Same App 20090315156 - Harper; Peter R.	2009-12-24
Low Inductance Ball Grid Array Device Having Chip Bumps on Substrate Vias App 20090289362 - Rhyner; Kenneth R. ; et al.	2009-11-26
Integrated Circuit Stacked Package Precursors And Stacked Packaged Devices And Systems Therefrom App 20090206455 - HARPER; PETER R. ; et al.	2009-08-20
Packaged Integrated Circuits Having Surface Mount Devices And Methods To Form Packaged Integrated Circuits App 20090166889 - Murugan; Rajen ; et al.	2009-07-02
BGA Package with Traces for Plating Pads Under the Chip App 20090115072 - RHYNER; KENNETH R. ; et al.	2009-05-07
Semiconductor Device Having Wafer Level Chip Scale Packaging Substrate Decoupling App 20090057889 - Murugan; Rajen M. ; et al.	2009-03-05
Method Of Forming A Stud Bump Over Passivation, And Related Device App 20090032939 - HARPER; Peter R. ; et al.	2009-02-05
Simplified Substrates for Semiconductor Devices in Package-on-Package Products App 20080258285 - Harper; Peter R. ; et al.	2008-10-23
Semiconductor device having a bond pad and method therefor Grant 7,271,013 - Yong , et al. September 18, 2	2007-09-18
Packaged integrated circuit having a heat spreader and method therefor App 20070031996 - Chopin; Sheila F. ; et al.	2007-02-08
Packaged IC using insulated wire Grant 7,138,328 - Downey , et al. November 21, 2	2006-11-21
Packaged integrated circuit having wire bonds and method therefor Grant 7,015,585 - Downey , et al. March 21, 2	2006-03-21
Inductive device including bond wires Grant 6,998,952 - Zhou , et al. February 14, 2	2006-02-14
Integrated circuit with test pad structure and method of testing Grant 6,937,047 - Tran , et al. August 30, 2	2005-08-30
Semiconductor device having a bond pad and method therefor Grant 6,921,979 - Downey , et al. July 26, 2	2005-07-26
Integrated circuit with test pad structure and method of testing App 20050030055 - Tran, Tu-Anh ; et al.	2005-02-10
Semiconductor device having a bond pad and method therefor Grant 6,844,631 - Yong , et al. January 18, 2	2005-01-18
Packaged IC using insulated wire App 20040217458 - Downey, Susan H. ; et al.	2004-11-04
Semiconductor package having optimized wire bond positioning Grant 6,812,580 - Wenzel , et al. November 2, 2	2004-11-02
Packaged integrated circuit having wire bonds and method therefor App 20040119168 - Downey, Susan H. ; et al.	2004-06-24
Packaged IC using insulated wire App 20040119172 - Downey, Susan H. ; et al.	2004-06-24
Semiconductor device having a bond pad and method therefor App 20030173668 - Downey, Susan H. ; et al.	2003-09-18
Semiconductor device having a bond pad and method therefor App 20030173667 - Yong, Lois E. ; et al.	2003-09-18