Harn; Ywh-Pyng
Patent Applications and Registrations
Patent applications and USPTO patent grants for Harn; Ywh-Pyng.The latest application filed is for "post-placement timing optimization of ic layout".
- Harn; Ywh-Pyng - Milpitas CA
| Patent | Date |
|---|---|
| Method for eliminating routing congestion in an IC layout Grant 7,225,116 - Harn May 29, 2 | 2007-05-29 |
| Post-placement timing optimization of IC layout Grant 7,137,093 - Harn November 14, 2 | 2006-11-14 |
| Post-placement timing optimization of IC layout App 20050034091 - Harn, Ywh-Pyng | 2005-02-10 |
| Method for eliminating routing congestion in an IC layout App 20040040007 - Harn, Ywh-Pyng | 2004-02-26 |
| Quadratic programming method for eliminating cell overlap and routing congestion in an IC layout Grant 6,668,365 - Harn December 23, 2 | 2003-12-23 |
| Quadratic programming method for eliminating cell overlap and routing congestion in an IC layout App 20030182649 - Harn, Ywh-Pyng | 2003-09-25 |
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