Harmon; David L.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Harmon; David L..The latest application filed is for "architectural construction technique".

Company Profile

2.21.11

Harmon; David L. - Saco ME US
Harmon; David L. - Essex VT
Harmon; David L. - Essex Junction VT US
Harmon; David L. - Cambridge MA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Architectural construction technique Grant 10,968,619 - Harmon April 6, 2	2021-04-06
Architectural Construction Technique App 20200018057 - Harmon; David L.	2020-01-16
Isolated zener diode, an integrated circuit incorporating multiple instances of the zener diode, a method of forming the zener diode and a design structure for the zener diode Grant 8,796,108 - Anderson , et al. August 5, 2	2014-08-05
Isolated Zener Diode, An Integrated Circuit Incorporating Multiple Instances Of The Zener Diode, A Method Of Forming The Zener Diode And A Design Structure For The Zener Diode App 20130299938 - Anderson; Frederick G. ; et al.	2013-11-14
Isolated Zener diode Grant 8,492,866 - Anderson , et al. July 23, 2	2013-07-23
Thin film resistors and methods of manufacture Grant 8,486,796 - Harmon , et al. July 16, 2	2013-07-16
Isolated Zener Diode App 20130175656 - Anderson; Frederick G. ; et al.	2013-07-11
Micro-electro-mechanical-system temperature sensor Grant 8,480,302 - Gill , et al. July 9, 2	2013-07-09
Radiant heat floor panel Grant D674,514 - Harmon January 15, 2	2013-01-15
Thin Film Resistors And Methods Of Manufacture App 20120126370 - HARMON; David L. ; et al.	2012-05-24
Micro-electro-mechanical-system Temperature Sensor App 20120076172 - Gill; Jason P. ; et al.	2012-03-29
Enhancement of performance of a conductive wire in a multilayered substrate Grant 7,511,378 - Gill , et al. March 31, 2	2009-03-31
Method of assessing potential for charging damage in SOI designs and structures for eliminating potential for damage Grant 7,132,318 - Bonges, III , et al. November 7, 2	2006-11-07
Enhancement of performance of a conductive wire in a multilayered substrate App 20060226142 - Gill; Jason P. ; et al.	2006-10-12
Enhancement of performance of a conductive wire in a multilayered substrate Grant 7,096,450 - Gill , et al. August 22, 2	2006-08-22
Method of assessing potential for charging damage in SOI designs and structures for eliminating potential for damage Grant 7,067,886 - Bonges, III , et al. June 27, 2	2006-06-27
Method of assessing potential for charging damage in SOI designs and structures for eliminating potential for damage App 20050098799 - Bonges, Henry A. III ; et al.	2005-05-12
Method Of Assessing Potential For Charging Damage In Soi Designs And Structures For Eliminating Potential For Damage App 20050093072 - Bonges, Henry A. III ; et al.	2005-05-05
Enhancement Of Performance Of A Conductive Wire In A Multilayered Substrate App 20040262031 - Gill, Jason P. ; et al.	2004-12-30
Selective deposition process Grant 5,618,379 - Armacost , et al. April 8, 1	1997-04-08
Fluorinated silicon nitride films Grant 5,462,812 - Nguyen , et al. October 31, 1	1995-10-31
Low temperature plasma oxidation process Grant 5,412,246 - Dobuzinsky , et al. May 2, 1	1995-05-02
Low temperature plasma oxidation process Grant 5,330,935 - Dobuzinsky , et al. July 19, 1	1994-07-19
Plasma enhanced CVD process for fluorinated silicon nitride films Grant 5,204,138 - Nguyen , et al. April 20, 1	1993-04-20
Reactive ion etching buffer mask Grant 5,118,384 - Harmon , et al. June 2, 1	1992-06-02

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