Harley; Eric C. T.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Harley; Eric C. T..The latest application filed is for "diamond shaped source drain epitaxy with underlying buffer layer".

Company Profile

0.11.12

Harley; Eric C. T. - Lagrangeville NY
Harley; Eric C. T. - Bel Air MD

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Diamond shaped source drain epitaxy with underlying buffer layer Grant 9,577,099 - Basker , et al. February 21, 2	2017-02-21
Epitaxial growth of material on source/drain regions of FinFET structure Grant 9,536,985 - Chudzik , et al. January 3, 2	2017-01-03
Uniform junction formation in FinFETs Grant 9,466,616 - Harley , et al. October 11, 2	2016-10-11
Diamond Shaped Source Drain Epitaxy With Underlying Buffer Layer App 20160268413 - Basker; Veeraraghavan S. ; et al.	2016-09-15
Uniform Junction Formation In Finfets App 20160181285 - Harley; Eric C.T. ; et al.	2016-06-23
Epitaxially Grown Silicon Germanium Channel Finfet With Silicon Underlayer App 20160163707 - Cheng; Kangguo ; et al.	2016-06-09
Uniform junction formation in FinFETs Grant 9,318,608 - Harley , et al. April 19, 2	2016-04-19
Epitaxial Growth Of Material On Source/drain Regions Of Finfet Structure App 20160093720 - Chudzik; Michael P. ; et al.	2016-03-31
Uniform Junction Formation In Finfets App 20160093740 - Harley; Eric C. T. ; et al.	2016-03-31
Epitaxially grown silicon germanium channel FinFET with silicon underlayer Grant 9,287,264 - Cheng , et al. March 15, 2	2016-03-15
Stressed Transistor With Improved Metastability App 20130134444 - Adam; Thomas N. ; et al.	2013-05-30
Stressed transistor with improved metastability Grant 8,361,859 - Adam , et al. January 29, 2	2013-01-29
METHODS OF INTEGRATING REVERSE eSiGe ON NFET AND SiGe CHANNEL ON PFET, AND RELATED STRUCTURE App 20120228716 - Harley; Eric C. T. ; et al.	2012-09-13
Methods of integrating reverse eSiGe on NFET and SiGe channel on PFET, and related structure Grant 8,232,186 - Harley , et al. July 31, 2	2012-07-31
Stressed Transistor With Improved Metastability App 20120112208 - ADAM; THOMAS N. ; et al.	2012-05-10
Method of forming source and drain of a field-effect-transistor and structure thereof Grant 8,084,788 - Holt , et al. December 27, 2	2011-12-27
Fabricating semiconductor structures Grant 8,080,451 - Adam , et al. December 20, 2	2011-12-20
Method For Fabricating Semiconductor Structures App 20100112762 - Adam; Thomas N. ; et al.	2010-05-06
Method Of Forming Source And Drain Of A Field-effect-transistor And Structure Thereof App 20100090288 - Holt; Judson R. ; et al.	2010-04-15
Method for fabricating a semiconductor structures and structures thereof Grant 7,687,804 - Adam , et al. March 30, 2	2010-03-30
METHODS OF INTEGRATING REVERSE eSiGe ON NFET AND SiGe CHANNEL ON PFET, AND RELATED STRUCTURE App 20090294801 - Harley; Eric C. T. ; et al.	2009-12-03
Method For Fabricating A Semiconductor Structures And Structures Thereof App 20090173941 - Adam; Thomas N. ; et al.	2009-07-09

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