loadpatents
name:-0.024646043777466
name:-0.0084171295166016
name:-0.013778924942017
HARAN; Mohit K. Patent Filings

HARAN; Mohit K.

Patent Applications and Registrations

Patent applications and USPTO patent grants for HARAN; Mohit K..The latest application filed is for "contact over active gate structures with etch stop layers for advanced integrated circuit structure fabrication".

Company Profile
13.6.19
  • HARAN; Mohit K. - Hillsboro OR
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Contact Over Active Gate Structures With Etch Stop Layers For Advanced Integrated Circuit Structure Fabrication
App 20220310516 - MADHAVAN; Atul ;   et al.
2022-09-29
Contact over active gate structures with etch stop layers for advanced integrated circuit structure fabrication
Grant 11,393,754 - Madhavan , et al. July 19, 2
2022-07-19
Contact Over Active Gate Structures With Tapered Gate Or Trench Contact For Advanced Integrated Circuit Structure Fabrication
App 20220190128 - WALLACE; Charles H. ;   et al.
2022-06-16
Transistor Arrangements With Stacked Trench Contacts And Gate Straps
App 20220190129 - Wei; Andy Chih-Hung ;   et al.
2022-06-16
Contact Over Active Gate Structures Using Directed Self-assembly For Advanced Integrated Circuit Structure Fabrication
App 20220102210 - NYHUS; Paul A. ;   et al.
2022-03-31
Gate Spacing In Integrated Circuit Structures
App 20220102148 - Wallace; Charles Henry ;   et al.
2022-03-31
Fabrication Of Gate-all-around Integrated Circuit Structures Having Pre-spacer Deposition Cut Gates
App 20220093592 - GULER; Leonard P. ;   et al.
2022-03-24
Plug & Trench Architectures For Integrated Circuits & Methods Of Manufacture
App 20220068707 - WALLACE; Charles H. ;   et al.
2022-03-03
Via Contact Patterning Method To Increase Edge Placement Error Margin
App 20220051975 - Haran; Mohit K. ;   et al.
2022-02-17
Via contact patterning method to increase edge placement error margin
Grant 11,211,324 - Haran , et al. December 28, 2
2021-12-28
Plug and trench architectures for integrated circuits and methods of manufacture
Grant 11,171,043 - Wallace , et al. November 9, 2
2021-11-09
Conductive via and metal line end fabrication and structures resulting therefrom
Grant 11,145,541 - Wallace , et al. October 12, 2
2021-10-12
Line Patterning In Integrated Circuit Devices
App 20210183761 - Patel; Reken ;   et al.
2021-06-17
Contact Over Active Gate Structures With Metal Oxide Layers To Inhibit Shorting
App 20210090990 - HOURANI; Rami ;   et al.
2021-03-25
Self-aligned Patterning With Colored Blocking And Structures Resulting Therefrom
App 20210090997 - HARAN; Mohit K. ;   et al.
2021-03-25
Via Contact Patterning Method To Increase Edge Placement Error Margin
App 20210082805 - Haran; Mohit K. ;   et al.
2021-03-18
1d Vertical Edge Blocking (veb) Via And Plug
App 20200388534 - GULER; Leonard P. ;   et al.
2020-12-10
Method To Repair Edge Placement Errors In A Semiconductor Device
App 20200373201 - WALLACE; Charles H. ;   et al.
2020-11-26
Conductive Via And Metal Line End Fabrication And Structures Resulting Therefrom
App 20200185271 - WALLACE; Charles H. ;   et al.
2020-06-11
Metal via processing schemes with via critical dimension (CD) control for back end of line (BEOL) interconnects and the resulting structures
Grant 10,636,700 - Nyhus , et al.
2020-04-28
Contact Over Active Gate Structures With Etch Stop Layers For Advanced Integrated Circuit Structure Fabrication
App 20200105672 - MADHAVAN; Atul ;   et al.
2020-04-02
Metal Via Processing Schemes With Via Critical Dimension (cd) Control For Back End Of Line (beol) Interconnects And The Resultin
App 20190259656 - NYHUS; Paul A. ;   et al.
2019-08-22
Plug & Trench Architectures For Integrated Circuits & Methods Of Manufacture
App 20190206728 - WALLACE; Charles H. ;   et al.
2019-07-04
Metal via processing schemes with via critical dimension (CD) control for back end of line (BEOL) interconnects and the resulting structures
Grant 10,319,625 - Nyhus , et al.
2019-06-11
Metal Via Processing Schemes With Via Critical Dimension (cd) Control For Back End Of Line (beol) Interconnects And The Resulting Structures
App 20180323100 - NYHUS; Paul A. ;   et al.
2018-11-08

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