Haraguchi; Yoshiyuki

Patent Applications and Registrations

Patent applications and USPTO patent grants for Haraguchi; Yoshiyuki.The latest application filed is for "communication device performing communication using two clock signals complementary to each other".

Company Profile

0.9.4

Haraguchi; Yoshiyuki - Tokyo JP
Haraguchi; Yoshiyuki - Hyogo JP

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Microprocessor processing specified instructions as operands Grant 6,862,680 - Haraguchi March 1, 2	2005-03-01
Semiconductor device capable of accurately producing internal multi-phase clock signal Grant 6,859,079 - Haraguchi , et al. February 22, 2	2005-02-22
Communication device performing communication using two clock signals complementary to each other App 20040157576 - Adachi, Kiyoshi ; et al.	2004-08-12
Integrated circuit Grant 6,754,865 - Haraguchi June 22, 2	2004-06-22
Semiconductor device capable of accurately producing internal multi-phase clock signal App 20040104753 - Haraguchi, Yoshiyuki ; et al.	2004-06-03
Semiconductor device having a semiconductor chip and a lead substrate connected with each other through pads and patterned lead wires without short-circuiting the pads App 20030098506 - Haraguchi, Yoshiyuki ; et al.	2003-05-29
Integrated circuit App 20020004923 - Haraguchi, Yoshiyuki	2002-01-10
Static type semiconductor memory with latch circuit amplifying read data read on a sub bit line pair and transferring the amplified read data to a main bit line pair and operation method thereof Grant 5,850,367 - Wada , et al. December 15, 1	1998-12-15
Static type semiconductor device operable at a low voltage with small power consumption Grant 5,677,889 - Haraguchi , et al. October 14, 1	1997-10-14
Semiconductor memory device including redundancy circuit for remedying defect in memory portion Grant 5,469,391 - Haraguchi November 21, 1	1995-11-21
Semiconductor memory device having redundancy memory cells shared among memory blocks Grant 5,446,692 - Haraguchi , et al. August 29, 1	1995-08-29
Semiconductor memory device adapted for preventing a test mode operation from undesirably occurring Grant 5,384,741 - Haraguchi , et al. January 24, 1	1995-01-24
Semiconductor memory device adapted for preventing a test mode operation from undesirably occurring Grant 5,305,267 - Haraguchi , et al. April 19, 1	1994-04-19

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