Hansen; Craig C.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Hansen; Craig C..The latest application filed is for "multiplier array processing system with enhanced utilization at lower precision".

Company Profile

0.15.1

Hansen; Craig C. - Los Altos CA
Hansen; Craig C. - Mountain View CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Configurable cache allowing cache-type and buffer-type access Grant RE43,798 - Hansen November 6, 2	2012-11-06
Multiplier array processing system with enhanced utilization at lower precision Grant 7,509,366 - Hansen March 24, 2	2009-03-24
Configurable cache allowing cache-type and buffer-type access Grant RE39,500 - Hansen February 27, 2	2007-02-27
Multiplier array processing system with enhanced utilization at lower precision App 20040015533 - Hansen, Craig C. ; et al.	2004-01-22
Multiplier array processing system with enhanced utilization at lower precision Grant 6,584,482 - Hansen , et al. June 24, 2	2003-06-24
Virtual memory system with local and global virtual address translation Grant 6,101,590 - Hansen August 8, 2	2000-08-08
General purpose, dynamic partitioning, programmable media processor Grant 6,006,318 - Hansen , et al. December 21, 1	1999-12-21
Multiplier array processing system with enhanced utilization at lower precision for group multiply and sum instruction Grant 5,953,241 - Hansen , et al. September 14, 1	1999-09-14
Method and system for facilitating byte ordering interfacing of a computer system Grant 5,819,117 - Hansen October 6, 1	1998-10-06
Technique of incorporating floating point information into processor instructions Grant 5,812,439 - Hansen September 22, 1	1998-09-22
DRAM with high bandwidth interface that uses packets and arbitration Grant 5,778,419 - Hansen , et al. July 7, 1	1998-07-07
Accessing system that reduces access times due to transmission delays and I/O access circuitry in a burst mode random access memory Grant 5,410,670 - Hansen , et al. April 25, 1	1995-04-25
Translation lookaside buffer shutdown scheme Grant 5,325,507 - Freitas , et al. June 28, 1	1994-06-28
Translation lookaside buffer shutdown scheme Grant 5,237,671 - Freitas , et al. August 17, 1	1993-08-17
Dual byte order computer architecture a functional unit for handling data sets with differnt byte orders Grant 4,959,779 - Weber , et al. September 25, 1	1990-09-25
RISC computer with unaligned reference handling and method for the same Grant 4,814,976 - Hansen , et al. March 21, 1	1989-03-21

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