Hammerl, Erwin

Patent Applications and Registrations

Patent applications and USPTO patent grants for Hammerl, Erwin.The latest application filed is for "method for checking the functioning of memory cells of an integrated semiconductor memory".

Company Profile

0.14.1

Hammerl, Erwin - Zangberg DE
Hammerl; Erwin - Stormville NY
Hammerl; Erwin - Emmerting DE
Hammerl; Erwin - Emerting DE
Hammerl; Erwin - Stromville NY

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Method for checking the functioning of memory cells of an integrated semiconductor memory App 20020026608 - Daehn, Wilfried ; et al.	2002-02-28
Method of controllably forming a LOCOS oxide layer over a portion of a vertically extending sidewall of a trench extending into a semiconductor substrate Grant 6,153,474 - Ho , et al. November 28, 2	2000-11-28
Shallow trench isolation (STI) with bilayer of oxide-nitride for VLSI applications Grant 6,140,208 - Agahi , et al. October 31, 2	2000-10-31
Nitride cap formation in a DRAM trench capacitor Grant 5,937,292 - Hammerl , et al. August 10, 1	1999-08-10
Three-dimensional device layout with sub-groundrule features Grant 5,893,735 - Stengl , et al. April 13, 1	1999-04-13
Buried strap formation in a DRAM trench capacitor Grant 5,844,266 - Stengl , et al. December 1, 1	1998-12-01
Microelectronic component and process for its production Grant 5,828,076 - Gossner , et al. October 27, 1	1998-10-27
Buried-strap formation in a dram trench capacitor Grant 5,827,765 - Stengl , et al. October 27, 1	1998-10-27
Three-dimensional device layout having a trench capacitor Grant 5,792,685 - Hammerl , et al. August 11, 1	1998-08-11
Application of thin crystalline Si.sub.3 N.sub.4 liners in shallow trench isolation (STI) structures Grant 5,747,866 - Ho , et al. May 5, 1	1998-05-05
Nitride cap formation in a DRAM trench capacitor Grant 5,717,628 - Hammerl , et al. February 10, 1	1998-02-10
Process for forming deep trench DRAMs with sub-groundrule gates Grant 5,674,769 - Alsmeier , et al. October 7, 1	1997-10-07
Controlled recrystallization of buried strap in a semiconductor memory device Grant 5,670,805 - Hammerl , et al. September 23, 1	1997-09-23
Storage node process for deep trench-based DRAM Grant 5,656,535 - Ho , et al. August 12, 1	1997-08-12
Shallow trench isolation with thin nitride liner Grant 5,447,884 - Fahey , et al. September 5, 1	1995-09-05

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