Halo LSI, Inc.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Halo LSI, Inc..The latest application filed is for "high density vertical structure nitride flash memory".

Company Profile

0.57.42

Halo LSI, Inc. - Hillsboro OR US
Halo LSI, Inc. -
Halo LSI, Inc. - Wappingers Falls NY
Halo LSI, Inc. - Wappinger Falls NY
Halo LSI, Inc. - Wappingers Fall NJ
Halo LSI, Inc. - Wapperings Falls NY

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
High density vertical structure nitride flash memory Grant 9,153,592 - Ogura , et al. October 6, 2	2015-10-06
Complementary reference method for high reliability trap-type non-volatile memory Grant 9,123,419 - Ogura , et al. September 1, 2	2015-09-01
High Density Vertical Structure Nitride Flash Memory App 20140219030 - Ogura; Seiki ; et al.	2014-08-07
Twin MONOS Array for High Speed Application App 20140133244 - Satoh; Kimihiro ; et al.	2014-05-15
Twin MONOS Array for High Speed Application App 20140133245 - Satoh; Kimihiro ; et al.	2014-05-15
High density vertical structure nitride flash memory Grant 8,710,576 - Ogura , et al. April 29, 2	2014-04-29
Twin MONOS array for high speed application Grant 8,633,544 - Satoh , et al. January 21, 2	2014-01-21
Complementary Reference Method for High Reliability Trap-Type Non-Volatile Memory App 20130094299 - Ogura; Nori ; et al.	2013-04-18
Complementary Reference Method for High Reliability Trap-Type Non-Volatile Memory App 20130094303 - Ogura; Nori ; et al.	2013-04-18
Complementary reference method for high reliability trap-type non-volatile memory Grant 8,325,542 - Ogura , et al. December 4, 2	2012-12-04
High speed operation method for twin MONOS metal bit array Grant 8,174,885 - Ogura , et al. May 8, 2	2012-05-08
Trap-charge non-volatile switch connector for programmable logic Grant 8,139,410 - Ogura , et al. March 20, 2	2012-03-20
Trap-charge non-volatile switch connector for programmable logic Grant 8,089,809 - Ogura , et al. January 3, 2	2012-01-03
Trap-charge non-volatile switch connector for programmable logic Grant 8,027,198 - Ogura , et al. September 27, 2	2011-09-27
Trap-charge non-volatile switch connector for programmable logic Grant 8,023,326 - Ogura , et al. September 20, 2	2011-09-20
High speed operation method for Twin MONOS metal bit array App 20110205798 - Ogura; Tomoko ; et al.	2011-08-25
High speed operation method for twin MONOS metal bit array Grant 7,936,604 - Ogura , et al. May 3, 2	2011-05-03
Complementary Reference method for high reliability trap-type non-volatile memory App 20100046302 - Ogura; Nori ; et al.	2010-02-25
Trench monos memory cell and array App 20090251973 - Satoh; Kimihiro	2009-10-08
Referencing scheme for trap memory Grant 7,447,077 - Ogura , et al. November 4, 2	2008-11-04
Twin insulator charge storage device operation and its fabrication method Grant 7,411,247 - Ogura , et al. August 12, 2	2008-08-12
Twin MONOS array for high speed application App 20080186763 - Satoh; Kimihiro ; et al.	2008-08-07
Twin insulator charge storage device operation and its fabrication method Grant 7,394,703 - Ogura , et al. July 1, 2	2008-07-01
Twin insulator charge storage device operation and its fabrication method Grant 7,391,653 - Ogura , et al. June 24, 2	2008-06-24
Twin insulator charge storage device operation and its fabrication method Grant 7,382,659 - Ogura , et al. June 3, 2	2008-06-03
Twin insulator charge storage device operation and its fabrication method Grant 7,382,662 - Ogura , et al. June 3, 2	2008-06-03
Twin insulator charge storage device operation and its fabrication method Grant 7,359,250 - Ogura , et al. April 15, 2	2008-04-15
Twin MONOS array for high speed application Grant 7,352,033 - Satoh , et al. April 1, 2	2008-04-01
Non-volatile memory dynamic operations Grant 7,301,820 - Ogura , et al. November 27, 2	2007-11-27
Continuous pressed laminates App 20070193683 - Huusken; Robert	2007-08-23
Nonvolatile memory array organization and usage Grant 7,190,603 - Ogura , et al. March 13, 2	2007-03-13
Twin MONOS array for high speed application App 20070047309 - Satoh; Kimihiro ; et al.	2007-03-01
High speed operation method for twin MONOS metal bit array App 20070047307 - Ogura; Tomoko ; et al.	2007-03-01
Referencing scheme for trap memory App 20070030745 - Ogura; Tomoko ; et al.	2007-02-08
Twin insulator charge storage device operation and its fabrication method Grant 7,170,132 - Ogura , et al. January 30, 2	2007-01-30
Twin insulator charge storage device operation and its fabrication method App 20060227622 - Ogura; Seiki ; et al.	2006-10-12
Stitch and select implementation in twin MONOS array Grant 7,118,961 - Ogura , et al. October 10, 2	2006-10-10
Twin insulator charge storage device operation and its fabrication method App 20060221706 - Ogura; Seiki ; et al.	2006-10-05
Twin insulator charge storage device operation and its fabrication method App 20060203562 - Ogura; Seiki ; et al.	2006-09-14
Twin insulator charge storage device operation and its fabrication method App 20060187709 - Ogura; Seiki ; et al.	2006-08-24
Fast program to program verify method Grant 7,046,553 - Ogura , et al. May 16, 2	2006-05-16
Twin insulator charge storage device operation and its fabrication method Grant 7,046,556 - Ogura , et al. May 16, 2	2006-05-16
Non-volatile semiconductor memory and driving method Grant 7,031,192 - Park , et al. April 18, 2	2006-04-18
Array architecture and operation methods for a nonvolatile memory Grant 7,006,378 - Saito , et al. February 28, 2	2006-02-28
Method of sense and program verify without a reference cell for non-volatile semiconductor memory Grant 6,999,345 - Park , et al. February 14, 2	2006-02-14
Twin NAND device structure, array operations and fabrication method Grant 6,998,658 - Ogura , et al. February 14, 2	2006-02-14
Twin insulator charge storage device operation and its fabrication method App 20050164451 - Ogura, Seiki ; et al.	2005-07-28
Twin insulator charge storage device operation and its fabrication method App 20050145928 - Ogura, Seiki ; et al.	2005-07-07
High efficiency triple well charge pump circuit Grant 6,914,791 - Park , et al. July 5, 2	2005-07-05
Twin insulator charge storage device operation and its fabrication method Grant 6,900,098 - Ogura , et al. May 31, 2	2005-05-31
Decoder circuit with function of plural series bit line selection Grant 6,876,596 - Kirihara April 5, 2	2005-04-05
Fast program to program verify method Grant 6,856,545 - Ogura , et al. February 15, 2	2005-02-15
Simplified twin monos fabrication method with three extra masks to standard CMOS Grant 6,838,344 - Satoh , et al. January 4, 2	2005-01-04
Twin NAND device structure, array operations and fabrication method Grant 6,825,084 - Ogura , et al. November 30, 2	2004-11-30
Simplified twin monos fabrication method with three extra masks to standard CMOS App 20040219751 - Satoh, Kimihiro ; et al.	2004-11-04
Fast program to program verify method Grant 6,807,105 - Ogura , et al. October 19, 2	2004-10-19
Stitch and select implementation in twin MONOS array App 20040166630 - Ogura, Tomoko ; et al.	2004-08-26
Stitch and select implementation in twin MONOS array Grant 6,759,290 - Ogura , et al. July 6, 2	2004-07-06
Simplified twin monos fabrication method with three extra masks to standard CMOS Grant 6,756,271 - Satoh , et al. June 29, 2	2004-06-29
Twin NAND device structure, array operations and fabrication method App 20040092066 - Ogura, Seiki ; et al.	2004-05-13
CG-WL voltage boosting scheme for twin MONOS Grant 6,735,118 - Ogura , et al. May 11, 2	2004-05-11
Twin NAND device structure, array operations and fabrication method App 20040087087 - Ogura, Seiki ; et al.	2004-05-06
Process for making and programming and operating a dual-bit multi-level ballistic flash memory Grant 6,714,456 - Ogura , et al. March 30, 2	2004-03-30
Twin MONOS cell fabrication method and array organization Grant 6,707,079 - Satoh , et al. March 16, 2	2004-03-16
Twin NAND device structure, array operations and fabrication method Grant 6,670,240 - Ogura , et al. December 30, 2	2003-12-30
Bit line decoding scheme and circuit for dual bit memory with a dual bit selection Grant 6,643,172 - Ogura November 4, 2	2003-11-04
Fast program to program verify method Grant 6,636,439 - Ogura , et al. October 21, 2	2003-10-21
Control gate decoder for twin MONOS memory with two bit erase capability Grant 6,636,438 - Ogura , et al. October 21, 2	2003-10-21
Twin MONOS array metal bit organization and single cell operation Grant 6,631,088 - Ogura , et al. October 7, 2	2003-10-07
Bit line decoding scheme and circuit for dual bit memory array Grant 6,631,089 - Ogura , et al. October 7, 2	2003-10-07
Fast program to program verify method App 20030185053 - Ogura, Seiki ; et al.	2003-10-02
Fast program to program verify method Grant 6,628,546 - Ogura , et al. September 30, 2	2003-09-30
Fast program to program verify method Grant 6,628,547 - Ogura , et al. September 30, 2	2003-09-30
Fast program to program verify method Grant 6,611,461 - Ogura , et al. August 26, 2	2003-08-26
Twin MONOS cell fabrication method and array organization App 20030143792 - Satoh, Kimihiro ; et al.	2003-07-31
High voltage level shifter Grant 6,600,357 - Kirihara July 29, 2	2003-07-29
Fast program to program verify method App 20030128588 - Ogura, Seiki ; et al.	2003-07-10
Fast program to program verify method App 20030123308 - Ogura, Seiki ; et al.	2003-07-03
Fast program to program verify method App 20030123291 - Ogura, Seiki ; et al.	2003-07-03
Fast program to program verify method App 20030123290 - Ogura, Seiki ; et al.	2003-07-03
Fast program to program verify method App 20030123292 - Ogura, Seiki ; et al.	2003-07-03
Fast program to program verify method App 20030123293 - Ogura, Seiki ; et al.	2003-07-03
Data programming implementation for high efficiency CHE injection Grant 6,567,314 - Ogura , et al. May 20, 2	2003-05-20
Control gate decoder for twin MONOS memory with two bit erase capability App 20030079540 - Ogura, Tomoko	2003-05-01
Fast program to program verify method Grant 6,549,463 - Ogura , et al. April 15, 2	2003-04-15
Bit line decoding scheme and circuit for dual bit memory with a dual bit selection App 20030031048 - Ogura, Tomoko	2003-02-13
Twin MONOS array metal bit organization and single cell operation App 20030022441 - Ogura, Seiki ; et al.	2003-01-30
CG-WL voltage boosting scheme for twin MONOS App 20030007387 - Ogura, Nori ; et al.	2003-01-09
Nonvolatile memory cell, operating method of the same and nonvolatile memory array App 20020149061 - Ogura, Seiki O. ; et al.	2002-10-17
Nonvolatile memory cell, operating method of the same and nonvolatile memory array App 20020149060 - Ogura, Seiki O. ; et al.	2002-10-17
Twin MONOS memory cell usage for wide program Grant 6,459,622 - Ogura , et al. October 1, 2	2002-10-01
Twin Monos Memory Cell Usage For Wide Program App 20020131304 - Ogura, Seiki ; et al.	2002-09-19
Erasing methods by hot hole injection to carrier trap sites of a nonvolatile memory Grant 6,418,062 - Hayashi , et al. July 9, 2	2002-07-09

Company Registrations

SEC

0001166476

HALO LSI INC