Halliyal; Arvind

Patent Applications and Registrations

Patent applications and USPTO patent grants for Halliyal; Arvind.The latest application filed is for "buried silicide local interconnect with sidewall spacers and method for making the same".

Company Profile

0.77.9

Halliyal; Arvind - Cupertino CA
Halliyal; Arvind - Sunnyvale CA
Halliyal; Arvind - Cuptertino CA
Halliyal; Arvind - Cuppertino CA
Halliyal; Arvind - Durham NC
Halliyal; Arvind - Newark DE

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Memory devices containing a high-K dielectric layer Grant 8,691,647 - Zheng , et al. April 8, 2	2014-04-08
Buried silicide local interconnect with sidewall spacers and method for making the same Grant 8,368,219 - Halliyal , et al. February 5, 2	2013-02-05
Buried Silicide Local Interconnect With Sidewall Spacers And Method For Making The Same App 20120038051 - Halliyal; Arvind ; et al.	2012-02-16
Buried silicide local interconnect with sidewall spacers and method for making the same Grant 8,049,334 - Halliyal , et al. November 1, 2	2011-11-01
Buried silicide local interconnect with sidewall spacers and method for making the same Grant 7,786,003 - Halliyal , et al. August 31, 2	2010-08-31
Nitridation of gate oxide by laser processing Grant 7,670,936 - Halliyal , et al. March 2, 2	2010-03-02
Semiconductor memory with data retention liner Grant 7,297,592 - Ngo , et al. November 20, 2	2007-11-20
Method of formation of gate stack spacer and charge storage materials having reduced hydrogen content in charge trapping dielectric flash memory device Grant 7,163,860 - Kamal , et al. January 16, 2	2007-01-16
Integrated ONO processing for semiconductor devices using in-situ steam generation (ISSG) process Grant 7,115,469 - Halliyal , et al. October 3, 2	2006-10-03
Scatterometry and acoustic based active control of thin film deposition process Grant 7,079,975 - Halliyal , et al. July 18, 2	2006-07-18
Memory with improved charge-trapping dielectric layer Grant 7,074,677 - Halliyal , et al. July 11, 2	2006-07-11
ONO fabrication process for increasing oxygen content at bottom oxide-substrate interface in flash memory devices Grant 7,033,957 - Shiraiwa , et al. April 25, 2	2006-04-25
UV-blocking layer for reducing UV-induced charging of SONOS dual-bit flash memory devices in BEOL processing Grant 7,018,896 - Ngo , et al. March 28, 2	2006-03-28
Laser thermal annealing methods for flash memory devices Grant 7,001,814 - Halliyal , et al. February 21, 2	2006-02-21
Memory cell structure having nitride layer with reduced charge loss and method for fabricating same Grant 6,992,370 - Kluth , et al. January 31, 2	2006-01-31
ONO fabrication process for reducing oxygen vacancy content in bottom oxide layer in flash memory devices Grant 6,969,886 - Park , et al. November 29, 2	2005-11-29
Flash memory device and method of fabrication thereof including a bottom oxide layer with two regions with different concentrations of nitrogen Grant 6,958,511 - Halliyal , et al. October 25, 2	2005-10-25
Process for fabrication of nitride layer with reduced hydrogen content in ONO structure in semiconductor device Grant 6,955,965 - Halliyal , et al. October 18, 2	2005-10-18
Laser thermal annealing method for forming semiconductor low-k dielectric layer Grant 6,955,997 - Halliyal , et al. October 18, 2	2005-10-18
Method of formation of semiconductor resistant to hot carrier injection stress Grant 6,949,433 - Hidehiko , et al. September 27, 2	2005-09-27
Process for fabrication of spacer layer with reduced hydrogen content in semiconductor device Grant 6,949,481 - Halliyal , et al. September 27, 2	2005-09-27
Laser thermal annealing to eliminate oxide voiding Grant 6,900,121 - Ngo , et al. May 31, 2	2005-05-31
Method of manufacturing a semiconductor memory with deuterated materials Grant 6,884,681 - Kamal , et al. April 26, 2	2005-04-26
Implant damage removal by laser thermal annealing Grant 6,872,643 - Halliyal , et al. March 29, 2	2005-03-29
Oxidizing pretreatment of ONO layer for flash memory Grant 6,858,496 - Ogle , et al. February 22, 2	2005-02-22
Preparation of composite high-K/standard-K dielectrics for semiconductor devices Grant 6,849,925 - Halliyal , et al. February 1, 2	2005-02-01
Monos device having buried metal silicide bit line Grant 6,828,199 - Ogura , et al. December 7, 2	2004-12-07
System and method for active control of BPSG deposition Grant 6,828,162 - Halliyal , et al. December 7, 2	2004-12-07
In situ monitoring of sheet resistivity of silicides during rapid thermal annealing using electrical methods Grant 6,815,229 - Halliyal , et al. November 9, 2	2004-11-09
Liner for semiconductor memories and manufacturing method therefor Grant 6,803,265 - Ngo , et al. October 12, 2	2004-10-12
ONO fabrication process for reducing oxygen vacancy content in bottom oxide layer in flash memory devices Grant 6,803,275 - Park , et al. October 12, 2	2004-10-12
Use of high-K dielectric material in modified ONO structure for semiconductor devices Grant 6,803,272 - Halliyal , et al. October 12, 2	2004-10-12
UV-blocking layer for reducing UV-induced charging of SONOS dual-bit flash memory devices in BEOL processing App 20040191989 - Ngo, Minh V. ; et al.	2004-09-30
Laser thermal annealing method for high dielectric constant gate oxide films Grant 6,783,591 - Halliyal , et al. August 31, 2	2004-08-31
UV-blocking layer for reducing UV-induced charging of SONOS dual-bit flash memory devices in BEOL Grant 6,774,432 - Ngo , et al. August 10, 2	2004-08-10
Interlayer dielectric void detection Grant 6,774,989 - Rangarajan , et al. August 10, 2	2004-08-10
Uv-blocking Layer For Reducing Uv-induced Charging Of Sonos Dual-bit Flash Memory Devices In Beol Processing App 20040151025 - Ngo, Minh V. ; et al.	2004-08-05
Method for semiconductor wafer planarization by CMP stop layer formation Grant 6,770,523 - Sahota , et al. August 3, 2	2004-08-03
Spacers with a graded dielectric constant for semiconductor devices having a high-K dielectric Grant 6,764,966 - En , et al. July 20, 2	2004-07-20
Stacked polysilicon layer for boron penetration inhibition Grant 6,762,454 - Ibok , et al. July 13, 2	2004-07-13
Acoustic microbalance for in-situ deposition process monitoring and control Grant 6,752,899 - Singh , et al. June 22, 2	2004-06-22
In-situ chemical composition monitor on wafer during plasma etching for defect control Grant 6,753,261 - Phan , et al. June 22, 2	2004-06-22
Precision high-K intergate dielectric layer Grant 6,750,066 - Cheung , et al. June 15, 2	2004-06-15
Process for reducing hydrogen contamination in dielectric materials in memory devices Grant 6,740,605 - Shiraiwa , et al. May 25, 2	2004-05-25
Doped copper interconnects using laser thermal annealing Grant 6,731,006 - Halliyal , et al. May 4, 2	2004-05-04
Gate oxide thickness measurement and control using scatterometry Grant 6,727,995 - Halliyal , et al. April 27, 2	2004-04-27
Method of forming reliable Cu interconnects Grant 6,727,176 - Ngo , et al. April 27, 2	2004-04-27
Monitoring of concentration of nitrogen in nitrided gate oxides, and gate oxide interfaces Grant 6,721,046 - Halliyal , et al. April 13, 2	2004-04-13
Method of forming flash memory having pre-interpoly dielectric treatment layer Grant 6,716,702 - Ogle, Jr. , et al. April 6, 2	2004-04-06
Process for treating ONO dielectric film of a floating gate memory cell Grant 6,709,927 - Ogle, Jr. , et al. March 23, 2	2004-03-23
Interfacial barrier layer in semiconductor devices with high-K gate dielectric material Grant 6,693,004 - Halliyal , et al. February 17, 2	2004-02-17
Replacing layers of an intergate dielectric layer with high-K material for improved scalability Grant 6,693,321 - Zheng , et al. February 17, 2	2004-02-17
Use of high-k dielectric materials in modified ONO structure for semiconductor devices Grant 6,674,138 - Halliyal , et al. January 6, 2	2004-01-06
Semiconductor memory with deuterated materials Grant 6,670,241 - Kamal , et al. December 30, 2	2003-12-30
Etch damage repair with thermal annealing Grant 6,667,243 - Ramsbey , et al. December 23, 2	2003-12-23
Memory manufacturing process using bitline rapid thermal anneal Grant 6,653,191 - Yang , et al. November 25, 2	2003-11-25
Preparation of composite high-K/standard-K dielectrics for semiconductor devices Grant 6,645,882 - Halliyal , et al. November 11, 2	2003-11-11
Integrated process for depositing layer of high-K dielectric with in-situ control of K value and thickness of high-K dielectric layer Grant 6,642,066 - Halliyal , et al. November 4, 2	2003-11-04
Use of high-K dielectric material in modified ONO structure for semiconductor devices Grant 6,642,573 - Halliyal , et al. November 4, 2	2003-11-04
X-ray reflectance system to determine suitability of SiON ARC layer Grant 6,633,392 - Singh , et al. October 14, 2	2003-10-14
Nitriding pretreatment of ONO nitride for oxide deposition Grant 6,620,705 - Ogle , et al. September 16, 2	2003-09-16
Memory wordline hard mask Grant 6,617,215 - Halliyal , et al. September 9, 2	2003-09-09
Semiconductor device with metal gate electrode and silicon oxynitride spacer Grant 6,605,848 - Ngo , et al. August 12, 2	2003-08-12
Process integration of electrical thickness measurement of gate oxide and tunnel oxides by corona discharge technique Grant 6,593,748 - Halliyal , et al. July 15, 2	2003-07-15
Oxide/nitride or oxide/nitride/oxide thickness measurement using scatterometry Grant 6,589,804 - Halliyal , et al. July 8, 2	2003-07-08
Integrated process for fabrication of graded composite dielectric material layers for semiconductor devices Grant 6,586,349 - Jeon , et al. July 1, 2	2003-07-01
Monos device having buried metal silicide bit line App 20030119314 - Ogura, Jusuke ; et al.	2003-06-26
Semiconductor device with metal gate electrode and silicon oxynitride spacer App 20030098487 - Ngo, Minh Van ; et al.	2003-05-29
Gate array with multiple dielectric properties and method for forming same Grant 6,563,183 - En , et al. May 13, 2	2003-05-13
Method of forming reliable Cu interconnects App 20030087522 - Ngo, Minh Van ; et al.	2003-05-08
Method of forming flash memory having pre-interpoly dielectric treatment layer App 20030071304 - Ogle, Robert B. JR. ; et al.	2003-04-17
Non-volatile memory dielectric as charge pump dielectric Grant 6,548,855 - Ramsbey , et al. April 15, 2	2003-04-15
Non volatile dielectric memory cell structure with high dielectric constant capacitive coupling layer App 20030062567 - Zheng, Wei ; et al.	2003-04-03
Silicon-starved PECVD method for metal gate electrode dielectric spacer Grant 6,509,282 - Ngo , et al. January 21, 2	2003-01-21
In-situ thickness measurement for use in semiconductor processing App 20020142493 - Halliyal, Arvind ; et al.	2002-10-03
Non-reducing process for deposition of polysilicon gate electrode over high-K gate dielectric material Grant 6,451,641 - Halliyal , et al. September 17, 2	2002-09-17
Process for optimizing pocket implant profile by RTA implant annealing for a non-volatile semiconductor device Grant 6,410,388 - Kluth , et al. June 25, 2	2002-06-25
Process for fabricating an ONO structure having a silicon-rich silicon nitride layer Grant 6,406,960 - Hopper , et al. June 18, 2	2002-06-18
Nitridation process for fabricating an ONO floating-gate electrode in a two-bit EEPROM device Grant 6,319,775 - Halliyal , et al. November 20, 2	2001-11-20
Flash memory having a treatment layer disposed between an interpoly dielectric structure and method of forming Grant 6,306,777 - Ogle, Jr. , et al. October 23, 2	2001-10-23
Method of fabricating an ONO dielectric by nitridation for MNOS memory cells Grant 6,248,628 - Halliyal , et al. June 19, 2	2001-06-19
Process for fabricating an ONO floating-gate electrode in a two-bit EEPROM device using rapid-thermal-chemical-vapor-deposition Grant 6,180,538 - Halliyal , et al. January 30, 2	2001-01-30
Light-absorbing dielectric compositions Grant 5,393,465 - Drozdyk , et al. February 28, 1	1995-02-28
Partially crystallizable glass compositions Grant 5,210,057 - Haun , et al. May 11, 1	1993-05-11