| Patent | Date |
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Circuit for addition of multiple binary numbers
Grant 10,528,323 - Beck , et al. J | 2020-01-07 |
Integrated circuit chip and a method for testing the same
Grant 10,317,465 - Haller , et al. | 2019-06-11 |
Circuit For Addition Of Multiple Binary Numbers
App 20190034165 - BECK; Manuel ; et al. | 2019-01-31 |
Circuit for addition of multiple binary numbers
Grant 10,168,991 - Beck , et al. J | 2019-01-01 |
Integrated Circuit Chip And A Method For Testing The Same
App 20180231607 - Haller; Wilhelm ; et al. | 2018-08-16 |
Detecting circuit design flaws based on timing analysis
Grant 10,031,995 - Haller , et al. July 24, 2 | 2018-07-24 |
Integrated circuit chip and a method for testing the same
Grant 10,006,965 - Haller , et al. June 26, 2 | 2018-06-26 |
Circuit For Addition Of Multiple Binary Numbers
App 20180088907 - BECK; Manuel ; et al. | 2018-03-29 |
Detecting Circuit Design Flaws Based On Timing Analysis
App 20170083658 - Haller; Wilhelm ; et al. | 2017-03-23 |
Integrated Circuit Chip And A Method For Testing The Same
App 20170003345 - Haller; Wilhelm ; et al. | 2017-01-05 |
Integrated circuit chip and a method for testing the same
Grant 9,506,986 - Haller , et al. November 29, 2 | 2016-11-29 |
Method and system to fix early mode slacks in a circuit design
Grant 9,058,456 - Haller , et al. June 16, 2 | 2015-06-16 |
Integrated Circuit Chip and a Method for Testing the Same
App 20150160293 - Haller; Wilhelm ; et al. | 2015-06-11 |
Method and system for repartitioning a hierarchical circuit design
Grant 8,701,059 - Gaugler , et al. April 15, 2 | 2014-04-15 |
Method And System To Fix Early Mode Slacks In A Circuit Design
App 20140089880 - Haller; Wilhelm ; et al. | 2014-03-27 |
Method and decimal arithmetic logic unit structure to generate a magnitude result of a mathematic
Grant 8,612,500 - Haller , et al. December 17, 2 | 2013-12-17 |
Method And System For Repartitioning A Hierarchical Circuit Design
App 20130239075 - Gaugler; Elmar ; et al. | 2013-09-12 |
Simd Accelerator For Data Comparison
App 20130227250 - Haller; Wilhelm ; et al. | 2013-08-29 |
Method and system for repartitioning a hierarchical circuit design
Grant 8,516,417 - Gaugler , et al. August 20, 2 | 2013-08-20 |
Early noise detection and noise aware routing in circuit design
Grant 8,423,940 - Daellenbach , et al. April 16, 2 | 2013-04-16 |
Early Noise Detection And Noise Aware Routing In Circuit Design
App 20130047130 - Daellenbach; Lukas ; et al. | 2013-02-21 |
Method and system for placement of electronic circuit components in integrated circuit design
Grant 8,302,056 - Gaugler , et al. October 30, 2 | 2012-10-30 |
Fast routing of custom macros
Grant 8,286,115 - Wetter , et al. October 9, 2 | 2012-10-09 |
Adder structure with midcycle latch for power reduction
Grant 8,086,657 - Haller , et al. December 27, 2 | 2011-12-27 |
Carry-select adder structure and method to generate orthogonal signal levels
Grant 7,908,308 - Haller , et al. March 15, 2 | 2011-03-15 |
Method and System for Repartitioning a Hierarchical Circuit Design
App 20110035711 - Gaugler; Elmar ; et al. | 2011-02-10 |
Method and System for Placement of Electronic Circuit Components in Integrated Circuit Design
App 20110035712 - Gaugler; Elmar ; et al. | 2011-02-10 |
Fast Routing Of Custom Macros
App 20100146471 - Wetter; Holger ; et al. | 2010-06-10 |
Method for comparing two designs of electronic circuits
Grant 7,546,565 - Fenkes , et al. June 9, 2 | 2009-06-09 |
Method and placement tool for designing the layout of an electronic circuit
Grant 7,530,038 - Gristede , et al. May 5, 2 | 2009-05-05 |
Method To Perform A Subtraction Of Two Operands In A Binary Arithmetic Unit Plus Arithmetic Unit To Perform Such A Method
App 20090112963 - Haller; Wilhelm ; et al. | 2009-04-30 |
Novel Adder Structure with Midcycle Latch for Power Reduction
App 20080294706 - Haller; Wilhelm ; et al. | 2008-11-27 |
Adder structure with midcycle latch for power reduction
Grant 7,406,495 - Haller , et al. July 29, 2 | 2008-07-29 |
Method And Decimal Arithmetic Logic Unit Structure To Generate A Magnitude Result of a Mathematic
App 20080177816 - Haller; Wilhelm ; et al. | 2008-07-24 |
Method for comparing two designs of electronic circuits
App 20080172640 - Fenkes; Joachim ; et al. | 2008-07-17 |
Method To Perform A Subtraction Of Two Operands In A Binary Arithmetic Unit Plus Arithmetic Unit To Perform Such A Method
App 20080071852 - Haller; Wilhelm ; et al. | 2008-03-20 |
Carry-Select Adder Structure and Method to Generate Orthogonal Signal Levels
App 20080046498 - Haller; Wilhelm ; et al. | 2008-02-21 |
Midcycle latch for power saving and switching reduction
Grant 7,224,190 - Haller , et al. May 29, 2 | 2007-05-29 |
Method and Placement Tool for Designing the Layout of an Electronic Circuit
App 20070083837 - Gristede; George D. ; et al. | 2007-04-12 |
Charge sharing reduction by applying intrinsic parallelism in complex dynamic domino type CMOS gates
Grant 7,095,252 - Haase , et al. August 22, 2 | 2006-08-22 |
Highly parallel structure for fast multi cycle binary and decimal adder unit
App 20060031279 - Haller; Wilhelm ; et al. | 2006-02-09 |
Midcycle latch for power saving and switching reduction
App 20050134316 - Haller, Wilhelm ; et al. | 2005-06-23 |
Novel adder structure with midcycle latch for power reduction
App 20050138103 - Haller, Wilhelm ; et al. | 2005-06-23 |
Charge sharing reduction by applying intrinsic parallelism in complex dynamic domino type CMOS gates
App 20050040861 - Haase, Michael ; et al. | 2005-02-24 |
Binary and decimal adder unit
Grant 6,292,819 - Bultmann , et al. September 18, 2 | 2001-09-18 |
Processing system having improved bi-directional serial clock communication circuitry
Grant 5,964,845 - Braun , et al. October 12, 1 | 1999-10-12 |
Carry-select adder with pre-counting of leading zero digits
Grant 5,875,123 - Dao Trong , et al. February 23, 1 | 1999-02-23 |
Method for executing branch instructions by processing loop end conditions in a second processor
Grant 5,634,047 - Getzlaff , et al. May 27, 1 | 1997-05-27 |
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