Haller; Gordon

Patent Applications and Registrations

Patent applications and USPTO patent grants for Haller; Gordon.The latest application filed is for "forming terminations in stacked memory arrays".

Company Profile

7.42.48

Haller; Gordon - Boise ID
Haller, Gordon - US

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Forming Terminations In Stacked Memory Arrays App 20210408029 - King; Matthew J. ; et al.	2021-12-30
Semiconductor Devices And Methods Of Fabrication App 20210366931 - Zhu; Hongbin ; et al.	2021-11-25
Formation of termination structures in stacked memory arrays Grant 11,177,279 - King , et al. November 16, 2	2021-11-16
Forming terminations in stacked memory arrays Grant 11,121,146 - King , et al. September 14, 2	2021-09-14
Semiconductor devices and methods of fabrication Grant 11,088,168 - Zhu , et al. August 10, 2	2021-08-10
Formation Of Termination Structures In Stacked Memory Arrays App 20200279867 - King; Matthew J. ; et al.	2020-09-03
Semiconductor Devices And Methods Of Fabrication App 20200227427 - Zhu; Hongbin ; et al.	2020-07-16
Formation of termination structures in stacked memory arrays Grant 10,658,380 - King , et al.	2020-05-19
Formation Of Termination Structures In Stacked Memory Arrays App 20200119040 - King; Matthew J. ; et al.	2020-04-16
Forming Terminations In Stacked Memory Arrays App 20200119036 - King; Matthew J. ; et al.	2020-04-16
Semiconductor devices and methods of fabrication Grant 10,608,004 - Zhu , et al.	2020-03-31
Drain select gate formation methods and apparatus Grant 10,242,995 - Zhu , et al.	2019-03-26
Memory devices and systems having reduced bit line to drain select gate shorting and associated methods Grant 10,134,758 - Zhu , et al. November 20, 2	2018-11-20
Semiconductor Devices And Methods Of Fabrication App 20180315766 - Zhu; Hongbin ; et al.	2018-11-01
Methods Of Tunnel Oxide Layer Formation In 3d Nand Memory Structures And Associated Devices App 20180294272 - Fan; Darwin ; et al.	2018-10-11
Semiconductor devices and methods of fabrication Grant 10,038,002 - Zhu , et al. July 31, 2	2018-07-31
Memory Devices And Systems Having Reduced Bit Line To Drain Select Gate Shorting And Associated Methods App 20180130819 - Zhu; Hongbin ; et al.	2018-05-10
Semiconductor Devices And Methods Of Fabrication App 20180108669 - Zhu; Hongbin ; et al.	2018-04-19
Drain Select Gate Formation Methods And Apparatus App 20180069015 - Zhu; Hongbin ; et al.	2018-03-08
Methods of tunnel oxide layer formation in 3D NAND memory structures and associated devices Grant 9,847,340 - Fan , et al. December 19, 2	2017-12-19
Drain select gate formation methods and apparatus Grant 9,842,847 - Zhu , et al. December 12, 2	2017-12-12
Memory devices and systems having reduced bit line to drain select gate shorting and associated methods Grant 9,741,734 - Zhu , et al. August 22, 2	2017-08-22
Memory Devices And Systems Having Reduced Bit Line To Drain Select Gate Shorting And Associated Methods App 20170170190 - Zhu; Hongbin ; et al.	2017-06-15
Forming source/drain zones with a dielectric plug over an isolation region between active regions Grant 9,530,683 - Hopkins , et al. December 27, 2	2016-12-27
Drain Select Gate Formation Methods And Apparatus App 20160233225 - Zhu; Hongbin ; et al.	2016-08-11
Forming air gaps in memory arrays and memory arrays with air gaps thus formed Grant 9,397,210 - Mathew , et al. July 19, 2	2016-07-19
Method of making a semiconductor device Grant 9,305,844 - Zhu , et al. April 5, 2	2016-04-05
Methods of fabricating fin structures Grant 9,281,402 - Tang , et al. March 8, 2	2016-03-08
Methods Of Tunnel Oxide Layer Formation In 3d Nand Memory Structures And Associated Devices App 20150279851 - Fan; Darwin ; et al.	2015-10-01
Semiconductor Devices Including Wisx App 20150162246 - Zhu; Hongbin ; et al.	2015-06-11
Forming Source/Drain Zones with a Delectric Plug Over an Isolation Region Between Active Regions App 20150064871 - Hopkins; John ; et al.	2015-03-05
Semiconductor devices including WiSX Grant 8,963,156 - Zhu , et al. February 24, 2	2015-02-24
Source/drain zones with a delectric plug over an isolation region between active regions and methods Grant 8,907,396 - Hopkins , et al. December 9, 2	2014-12-09
Methods Of Fabricating Fin Structures App 20140346613 - Tang; Sanh D. ; et al.	2014-11-27
Semiconductor Devices Including Wisx And Methods Of Fabrication App 20140239303 - Zhu; Hongbin ; et al.	2014-08-28
Methods of fabricating fin structures Grant 8,748,280 - Tang , et al. June 10, 2	2014-06-10
Forming Air Gaps In Memory Arrays And Memory Arrays With Air Gaps Thus Formed App 20140027832 - Mathew; James ; et al.	2014-01-30
Forming air gaps in memory arrays and memory arrays with air gaps thus formed Grant 8,569,130 - Mathew , et al. October 29, 2	2013-10-29
Methods of fabricating a memory device Grant 8,546,215 - Haller , et al. October 1, 2	2013-10-01
Methods Of Fabricating A Memory Device App 20130178025 - Haller; Gordon ; et al.	2013-07-11
Source/drain Zones With A Delectric Plug Over An Isolation Region Between Active Regions And Methods App 20130168756 - Hopkins; John ; et al.	2013-07-04
Forming Air Gaps In Memory Arrays And Memory Arrays With Air Gaps Thus Formed App 20130026600 - Matthew; James ; et al.	2013-01-31
Methods Of Fabricating A Memory Device App 20120231592 - Haller; Gordon ; et al.	2012-09-13
Methods of fabricating a memory device Grant 8,222,105 - Haller , et al. July 17, 2	2012-07-17
Methods Of Fabricating Fin Structures App 20120088349 - Tang; Sanh D. ; et al.	2012-04-12
Fin structures and methods of fabricating fin structures Grant 8,076,721 - Tang , et al. December 13, 2	2011-12-13
Methods of Making a Semiconductor Memory Device App 20110171802 - Tang; Sanh D. ; et al.	2011-07-14
Semiconductor Constructions and Transistors, and Methods of Forming Semiconductor Constructions and Transistors App 20110012182 - TANG; Sanh D. ; et al.	2011-01-20
Method and apparatus for a two-step resist soft bake to prevent ILD outgassing during semiconductor processing Grant 7,846,851 - Shirley , et al. December 7, 2	2010-12-07
Transistors Grant 7,825,462 - Tang , et al. November 2, 2	2010-11-02
Fin Structures And Methods Of Fabricating Fin Structures App 20100252886 - Tang; Sanh D. ; et al.	2010-10-07
Method, apparatus, and system for flash memory Grant 7,808,053 - Haller , et al. October 5, 2	2010-10-05
System and method for fabricating a fin field effect transistor Grant 7,745,319 - Tang , et al. June 29, 2	2010-06-29
Semiconductor Memory Device App 20100144107 - Haller; Gordon ; et al.	2010-06-10
Semiconductor memory device Grant 7,696,567 - Haller , et al. April 13, 2	2010-04-13
Integrated circuits Grant 7,687,857 - Tang , et al. March 30, 2	2010-03-30
One Transistor Memory Cell with Bias Gate App 20090311845 - Tang; Sanh D. ; et al.	2009-12-17
System for two-step resist soft bake to prevent ILD outgassing during semiconductor processing Grant 7,605,350 - Shirley , et al. October 20, 2	2009-10-20
One-transistor memory cell with bias gate Grant 7,589,995 - Tang , et al. September 15, 2	2009-09-15
Transistor devices, transistor structures and semiconductor constructions Grant 7,547,945 - Tang , et al. June 16, 2	2009-06-16
Methods of forming semiconductor constructions Grant 7,501,684 - Tang , et al. March 10, 2	2009-03-10
Method, Apparatus, And System For Flash Memory App 20080162781 - Haller; Gordon ; et al.	2008-07-03
Transistors App 20080142882 - Tang; Sanh D. ; et al.	2008-06-19
Integrated Circuits and Methods of Forming a Field Effect Transistor App 20080099847 - Tang; Sanh D. ; et al.	2008-05-01
One-transistor memory cell with bias gate App 20080061346 - Tang; Sanh D. ; et al.	2008-03-13
System and method for fabricating a fin field effect transistor App 20080050885 - Tang; Sanh D. ; et al.	2008-02-28
Integrated circuits and methods of forming a field effect transistor Grant 7,329,924 - Tang , et al. February 12, 2	2008-02-12
Integrated circuits and methods of forming a field effect transistor Grant 7,244,659 - Tang , et al. July 17, 2	2007-07-17
Integrated circuits and methods of forming a field effect transistor App 20070141771 - Tang; Sanh D. ; et al.	2007-06-21
Semiconductor memory device App 20070051997 - Haller; Gordon ; et al.	2007-03-08
Semiconductor constructions and transistors, and methods of forming semiconductor constructions and transistors App 20060261393 - Tang; Sanh D. ; et al.	2006-11-23
Integrated circuits and methods of forming a field effect transistor App 20060205128 - Tang; Sanh D. ; et al.	2006-09-14
Semiconductor constructions and transistors, and methods of forming semiconductor constructions and transistors App 20060043449 - Tang; Sanh D. ; et al.	2006-03-02
System for two-step resist soft bake to prevent ILD outgassing during semiconductor processing App 20060008758 - Shirley; Paul ; et al.	2006-01-12
Method to form a corrugated structure for enhanced capacitance Grant 6,927,445 - Thakur , et al. August 9, 2	2005-08-09
Method and apparatus for a two-step resist soft bake to prevent ILD outgassing during semiconductor processing App 20050164134 - Shirley, Paul ; et al.	2005-07-28
Method to form a corrugated structure for enhanced capacitance with plurality of boro-phospho silicate glass including germanium Grant 6,660,611 - Thakur , et al. December 9, 2	2003-12-09
Contact Plug App 20020093099 - JUENGLING, WERNER ; et al.	2002-07-18
Method to form a corrugated structure for enhanced capacitance App 20020093090 - Thakur, Randhir P.S. ; et al.	2002-07-18
Method to form a corrugated structure for enhanced capacitance App 20020045314 - Thakur, Randhir P.S. ; et al.	2002-04-18
Method to form a corrugated structure for enhanced capacitance Grant 6,346,455 - Thakur , et al. February 12, 2	2002-02-12
Method of forming contact plugs Grant 5,858,865 - Juengling , et al. January 12, 1	1999-01-12

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.